You are here:
PCIe 4.0 SerDes PHY
The Rambus 16 Gbps PCIe SerDes PHYs is a high-performance serial link subsystem. Optimized for power and area in challenging, high-loss channels typical of copper backplanes and long runs of cable, our 16G MPS PHYs are ideal for networking, telecom and data center systems.
特色
- Duplex lane configurations of x2, x4, and x35
- Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
- Support for AC-coupled interfaces
- Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
- BER of 10-15 for CEI11-LR/SR and BER of 10-12 for SFI, XFI, PCIe and Gbe protocolsA wide range of PLL multiplication supporting low reference clock frequenciesTight skew control of 2UI between lanes of the PMABuilt-in Self Test (BIST) with ATPG and AC/DC boundary scan supportBuilt-in PRBS pattern generation and checking for standalone loopback testingContinuous time linear equalizer (CTLe) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies
可交付内容
- PMA Hard Macro
- PCS-BIST Soft Macro
- Datasheet
- SoC integration guide
- Optional design integration and bring-up support services
Block Diagram of the PCIe 4.0 SerDes PHY
查看 PCIe 4.0 SerDes PHY 详细介绍：
- 查看 PCIe 4.0 SerDes PHY 完整数据手册
- 联系 PCIe 4.0 SerDes PHY 供应商
PCIe 4.0 SerDes PHY
- 32G Multi-protocol SerDes PHY
- PCI Express GEN 3/4 Port SERDES PHY - Samsung 7LPP
- 28Gbps Multi-Standard SerDes PHY
- Single Lane and Quad Lane 16Gbps PCIe4.0 PHY IP in TSMC 28HPC process
- Multi-Link Multi-Protocol SerDes - PHY IP for PCIe 3.0 TSMC 16FF+LL
- Multi-Link Multi-Protocol SerDes - PHY IP for PCIe 2.0 TSMC 16FF+GL