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PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface standard. Due to the support of an extra PLL control, reference clock control, and inbuilt power gating control, low power consumption is accomplished. Additionally, because the low power mode option is customizable, the PHY is extensively useful for a variety of settings with diverse power consumption considerations.
PCIe PHY functionality is verified in NC-Verilog simulation software using test bench written in Verilog HDL.
PCIe PHY functionality is verified in NC-Verilog simulation software using test bench written in Verilog HDL.
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Block Diagram of the PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
pcie3.0ip IP
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