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MIPI I3C Verification IP with IBI feature enabled

• Push-pull mode,
• Open drain switching,
• CCC, command

UCIe Verification IP

• Support latest PCIe Gen5/6 and CXL 2.0/3.0
• Device and Retimer supported
• Multiple stacks / multiple protocol

Synthesizable DDR5 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model

SGPIO Verification IP

• Compliant with SFF-8485 Specification for Serial GPIO (SGPIO) Bus revision 0.7.
• Full SGPIO Initiator and SGPIO Target functionality.

Simulation VIP for AMBA ATP

• Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
• Predefined protocol checkers to evaluate the compliance of the DUT model to protocol requirements

MIPI TWP Verification IP

• Compliant with MIPI TWP Specification version 1.1.
• Supports ATB interface.

CXL 3.0 Verification IP

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
• Unique development methodology to ensure the highest levels of quality.
• 24X5 customer support.

Simulation VIP for Ethernet 5G Network

• SyncE
• eCPRI

CXS a/b Verification IP

• Compliant with the CXS Version A specification
• Verification IP configurable as CXS ON-CHIP and OFF_CHIP Interconnect
• Support for different CXS Resets

RISC-V formal Verification IP

• Push-button, GUI based
• Efficient bug hunting
• Predictable run times for proving instruction-set-architecture

MIPI A-PHY Verification IP

• Compliant to MIPI A-PHY Specification Version 1.1 with APPI interface.
• Support all C-Port, D-Port, and Q-Port.

Simulation VIP for AMBA DTI

• Bypass Translation Mode Support
• Connect and Disconnect Message Group
• DTI-TBU Caching Module

PCIe Gen6 VIP

• Comprehensive support for PCI Express standard for 1.1, 2.1, 3.0, SR-IOV, SOP/PQI, and Intel PIPE PHY including BFMs for N-port Root Complex, Endpoint, SR-IOV Endpoint, N-port Switch, and PIPE-compliant PH

Source Code Test Suites PCIe

VC Verification IP for PCIe

SPI/MOTOROLA Verification IP

SPI (Serial Peripheral Interface) Verification IP

NVMe VIP

DDR5 Memory Model

Ethernet Verification IP (10/100M, 1 / 10 / 25 / 40 / 50 / 100 / 200 / 400 / 800G)

• Comprehensive support for IEEE 802.1 and 802.3 standards
• Multi-port MAC, PHY, Bridge models

SPI (Serial Peripheral Interface) Flash Verification IP

40G/100G Ethernet Verification IP

• Provides 40G as per IEEE Std 802.3
• Provides 100G as per IEEE Std 802.3
• Supports Energy Efficient Ethernet
• Supports all possible widths for PCS to Serdes interface

UART VMM based Verification IP

Verification IP I2S