Search for Verification IP

GDDR6 UVM Verification IP

• Fully compliance with JEDEC Specification JESD250A.
• Support DQ data rate up to 12 Gbps per pin.
• Support Low powe mode features.

USB4 Verification IP (VIP)

• Support verification of all protocol layers and configurations
• Callback-based error injection capability for creation of illegal stimulus from the VIP.

VC Verification IP for CPRI

• CPRI specification 7.0
• Single agent, can be configured as RE or REC
• Multiple ports, with master or slave characteristics

GDDR7 Memory Model

• Supports GDDR7 memory devices from all leading vendors.
• Supports 100% of GDDR7 protocol draft JEDEC specification.

TileLink Verification IP

• Supports TileLink Master, TileLink Slave, TileLink Interconnect, TileLink Monitor and TileLink Checker.

Ethernet-TSN Verification IP

• Faster testbench development and more complete verification of Ethernet-TSN designs
• Easy to use command interface simplifies testbench control and configuration of TX and RX

Gen Z Verification IP

• Multiple Physical Layers supported which can be selected as per medium
• Capable of Power Management and support for all low power states

SD Card Verification IP

• Compatible with all the versions V1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 6.10, 7.00
• Supports all Capacity of Memory i.e.
• Standard Capacity SD Memory Card (SDSC)

SD Express Card Verification IP

• Compliant to SD Specification v7.00
• SD Express card supports NVMe protocol over PCIe Interface
• Supports SD and PCIe Mode

TS5 Verification IP

• Implemented in native OpenVera, Verilog, SystemC and SystemVerilog.
• Supported RVM, AVM, VMM, OVM, UVM and non-standard verify env.

HBM2E Memory Model

• Supports HBM2E memory devices from all leading vendors.
• Supports 100% of HBM2E protocol standard specification.

OpenCAPI Verification IP

• Compliant with OpenCAPI Specification versions 3.0 and 3.1
• Complete OpenCAPI Tx/Rx functionality.
• Supports the Data Link Layer and Transaction Layer of OpenCAPI Specification.

VC Verification IP for I2C

Serial Peripheral Interface Verification IP

AMBA AXI4 Verification IP

Source Code Test Suites AXI Interconnect

UART UVM Verification IP

I2S Master and Slave OVM/UVM Verification IP

UART Verification IP (VIP)

I2C Master and Slave OVM/UVM Verification IP

• Highly Flexible, Independent and Configurable I2C Master VIP
• Proven against Silicon Proven VIP

VC Verification IP for UART

DRAM Memory Model - Synthesizable

Synopsys Verification IP for LPDDR4

• August 2014 JEDEC LPDDR4 Standard
• 4Gb to 32Gb densities and x16 SRAM devices

GDDR6 UVM Verification IP

• Fully compliance with JEDEC Specification JESD250A.
• Support DQ data rate up to 12 Gbps per pin.
• Support Low powe mode features.