English
New Verification IP
-
MPEG-2 TS Verification IP
- Full MPEG-2 TS Transmitter and Receiver functionality.
- Supports the combination of the video and audio coding methods defined in Parts 2 and 3 of ISO/IEC 13818
-
TileLink Verification IP (VIP)
- Plugs into existing verification environments
- Rapid test bench integration reduces time to first test
-
MIPI SPMI Verification IP (VIP)
- SystemVerilog coverage infrastructure for extendable coverage
- Callback-based error injection capability for creation of illegal stimulus from the VIP
-
Ethernet 100GPL (802.3ck) Verification IP (VIP)
- SV coverage infrastructure for extendable coverage
- Callback-based error injection capability for creation of illegal stimulus from the VIP
-
CXL Verification IP
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
-
Display Port 2.0 Verification IP
- Full Display port 2.0 source device and sink device functionality.
- Supports backward compatibility with previous versions upto DPv1.4a
-
Flash Octal SPI (OSPI) Verification IP
- Supports Extended SPI mode as well as Octal SDR and DDR mode (Single I/O and Octal I/O)
-
DisplayPort 2.0 Verification IP (VIP)
- Plugs into existing verification environments
- Rapid testbench integration reduces time to first test
- Incorporates expertise acquired through many prior applications
-
TPM Verification IP
- Full TPM master device and slave device functionality.
- Compliant to the Trusted Computing Group (TCG) Trusted Platform Module(TPM) Version 1.1b/1.2 and 2.0 Specification
-
GDDR6 UVM Verification IP
- Fully compliance with JEDEC Specification JESD250A.
- Support DQ data rate up to 12 Gbps per pin.
- Support Low powe mode features.
-
USB4 Verification IP (VIP)
- Support verification of all protocol layers and configurations
- Callback-based error injection capability for creation of illegal stimulus from the VIP.
-
VC Verification IP for CPRI
- CPRI specification 7.0
- Single agent, can be configured as RE or REC
- Multiple ports, with master or slave characteristics
Top Verification IP
-
1
PCIe End Point UVM Verification IP
- Independently controlled egress, ingress traffic, and support for all types of packets.
- PCIe and legacy interrupt support.
-
2
AMBA 3 APB Verification IP with compliance testsuite
-
3
Source Code Test Suites AXI Interconnect
-
4
Display Port 2.0 Verification IP
- Full Display port 2.0 source device and sink device functionality.
- Supports backward compatibility with previous versions upto DPv1.4a
-
5
Fully configurable Master, Slave or Monitor IP for verifying any AXI-based interface
-
6
Ethernet Verification IP
- Easy to set up and configure a testbench for validation of Ethernet designs.
- Simple testbench configuration of TX and RX Interfaces
- Included reference Scoreboards for Results Analysis
-
10
APB 4.0/3.0 UVM/OVM SV Master Verification IP
- Configurable DataSize
- Configurable PSELx
- Supports Unaligned Address access
-
11
Ethernet-TSN Verification IP
- Faster testbench development and more complete verification of Ethernet-TSN designs
- Easy to use command interface simplifies testbench control and configuration of TX and RX
-
12
I2C Master and Slave OVM/UVM Verification IP
- Highly Flexible, Independent and Configurable I2C Master VIP
- Proven against Silicon Proven VIP
¹ Top Verification IP Over the Last Two Weeks (Last update: Feb. 23)
IP Provider: Give the best exposure to your IPs, by listing your products for free in the world's largest Verification IP Catalog