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最新IP
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USB4 v2.0 Verification IP
- Fully compliant with USB4 specification v2.0 (October 2022) and Connection Manager version 2.0.
- Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.
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MASS Solution Verification IP
- Support full functionality of APHY as a physical layer
- Support Different PAL for multiple adaption layers for A-pkt conversion
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UCIe Verification IP
- Available in native SystemVerilog (UVM/OVM /VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
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TCP/TCPSW Verification IP
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
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Simulation VIP for MIPI SoundWire-I3S
- Support testbench language interfaces for SystemVerilog and UVM
- Generates constrained-random bus traffic with predefined error injection
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Ethernet Preemption Verification IP
- Provides Ethernet fully compliant to 802.3-2018 supporting all media independent interfaces for (1/10/25/40/50/100/200/400/800 G)
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MIPI A-PHY Verification IP
- Supports MIPI A-PHY specification 1.0 and 1.1
- Supports single lane and dual lane, point-to-point and serial communication technology
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Simulation VIP for UCIE
- Support testbench language interfaces for SystemVerilog, UVM
- Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
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MIPI I3C Verification IP with IBI feature enabled
- Push-pull mode,
- Open drain switching,
- CCC, command
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UCIe Verification IP
- Support latest PCIe Gen5/6 and CXL 2.0/3.0
- Device and Retimer supported
- Multiple stacks / multiple protocol
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Synthesizable DDR5 Bus Functional Model
- Fully JEDEC spec functionality compliant and reports any non-compliance issues
- Fully cycle accurate model
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SGPIO Verification IP
- Compliant with SFF-8485 Specification for Serial GPIO (SGPIO) Bus revision 0.7.
- Full SGPIO Initiator and SGPIO Target functionality.
热门IP
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1
USB4 v2.0 Verification IP
- Fully compliant with USB4 specification v2.0 (October 2022) and Connection Manager version 2.0.
- Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.
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2
eDP (Embedded DisplayPort) Verification IP
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3
Simulation VIP for UCIE
- Support testbench language interfaces for SystemVerilog, UVM
- Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
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10
JESD204B Verification IP
- Support device subclass0,subclass1 and subclass2.
- Supports serial data rate up to 12.5 Gbps.
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11
DisplayPort eDP Verification IP
- VESA DisplayPort 1.4, eDP 1.4b, DSC 1.2
- Verification of both transmitter/source and receiver/sink and PHY designs
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12
MIPI UniPro Verification IP
- Fully compliant with UniPro specification 1.41.00
- Supports TC0 and TC1 Traffic Classes
- Supports maximum of 4 lanes in each direction
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