1Kx32 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 1.1/2.5V
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最新IP
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MIPI I3C Verification IP with IBI feature enabled
- Push-pull mode,
- Open drain switching,
- CCC, command
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UCIe Verification IP
- Support latest PCIe Gen5/6 and CXL 2.0/3.0
- Device and Retimer supported
- Multiple stacks / multiple protocol
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Synthesizable DDR5 Bus Functional Model
- Fully JEDEC spec functionality compliant and reports any non-compliance issues
- Fully cycle accurate model
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SGPIO Verification IP
- Compliant with SFF-8485 Specification for Serial GPIO (SGPIO) Bus revision 0.7.
- Full SGPIO Initiator and SGPIO Target functionality.
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Simulation VIP for AMBA ATP
- Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
- Predefined protocol checkers to evaluate the compliance of the DUT model to protocol requirements
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MIPI TWP Verification IP
- Compliant with MIPI TWP Specification version 1.1.
- Supports ATB interface.
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CXL 3.0 Verification IP
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
- Unique development methodology to ensure the highest levels of quality.
- 24X5 customer support.
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Simulation VIP for Ethernet 5G Network
- SyncE
- eCPRI
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CXS a/b Verification IP
- Compliant with the CXS Version A specification
- Verification IP configurable as CXS ON-CHIP and OFF_CHIP Interconnect
- Support for different CXS Resets
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RISC-V formal Verification IP
- Push-button, GUI based
- Efficient bug hunting
- Predictable run times for proving instruction-set-architecture
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MIPI A-PHY Verification IP
- Compliant to MIPI A-PHY Specification Version 1.1 with APPI interface.
- Support all C-Port, D-Port, and Q-Port.
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Simulation VIP for AMBA DTI
- Bypass Translation Mode Support
- Connect and Disconnect Message Group
- DTI-TBU Caching Module
热门IP
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1
PCIe Gen6 VIP
- Comprehensive support for PCI Express standard for 1.1, 2.1, 3.0, SR-IOV, SOP/PQI, and Intel PIPE PHY including BFMs for N-port Root Complex, Endpoint, SR-IOV Endpoint, N-port Switch, and PIPE-compliant PH
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2
Source Code Test Suites PCIe
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3
VC Verification IP for PCIe
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7
DDR5 Memory Model
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8
Ethernet Verification IP (10/100M, 1 / 10 / 25 / 40 / 50 / 100 / 200 / 400 / 800G)
- Comprehensive support for IEEE 802.1 and 802.3 standards
- Multi-port MAC, PHY, Bridge models
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9
SPI (Serial Peripheral Interface) Flash Verification IP
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10
40G/100G Ethernet Verification IP
- Provides 40G as per IEEE Std 802.3
- Provides 100G as per IEEE Std 802.3
- Supports Energy Efficient Ethernet
- Supports all possible widths for PCS to Serdes interface
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11
UART VMM based Verification IP
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12
Verification IP I2S
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