English
New Verification IP
-
RISC-V formal Verification IP
- Push-button, GUI based
- Efficient bug hunting
- Predictable run times for proving instruction-set-architecture
-
MIPI A-PHY Verification IP
- Compliant to MIPI A-PHY Specification Version 1.1 with APPI interface.
- Support all C-Port, D-Port, and Q-Port.
-
AMBA DTI Verification IP (VIP)
- Bypass Translation Mode Support
- Connect and Disconnect Message Group
- DTI-TBU Caching Module
-
JESD204 Verification IP
- High Performance
- Richly Featured
- Easy to use
-
ARINC 664 Verification IP
- Supports IEEE 802.3 10/100 Mbit/s Full duplex Ethernet links
- Supports all word structures and protocol necessary to establish bus communication as per the specs.
-
PCIe Gen 6 Verification IP
- Compliant with PCI Express Specifications 6.0 v0.7(64GT/s), 5.0 v1.0(32GT/s), 4.0 v1.0 (16GT/s), 3.0 (8GT/s), 2.0 (5GT/s) and 1.1 (2.5GT/s).
-
Ethernet 10BASE-T1S Verification IP
- Faster testbench development and more complete verification of 10BASE-T1S designs.
-
Synthesizable LPDDR5 Bus Functional Model
- Fully JEDEC spec functionality compliant and reports any non-compliance issues
- Fully cycle accurate model
-
Ethernet Verification IP (10/100M, 1 / 10 / 25 / 40 / 50 / 100 / 200 / 400 / 800G)
- Comprehensive support for IEEE 802.1 and 802.3 standards
- Multi-port MAC, PHY, Bridge models
-
JTAG DTM Verification IP
- Compliant to RISC-V Debug Specification 0.13.2, JTAG DTM provided by SiFive, Inc.
-
FPU Verification IP
- Compliant to RISC-V Specification and IEEE 754 floating point standard.
- Configurable bits (half, single, double and quad precision).
-
RI5CY Verification IP
- Compliant to RI5CY specification for PULPmicroprocessor cores provided be Integrated Systems Lab, Inc.
Top Verification IP
-
1
VC Verification IP for AMBA 4 AXI
-
2
I2C Master and Slave OVM/UVM Verification IP
- Highly Flexible, Independent and Configurable I2C Master VIP
- Proven against Silicon Proven VIP
-
3
AMBA AXI4 Verification IP
-
4
I2C Verification IP
-
5
PCIe Gen 3 Verification IP
- Compliant with PCI Express Specifications 3.0 (8GT/s), 2.0
- (5GT/s) and 1.1 (2.5GT/s)
- x1/x2/x4/ x8/ x16 lanes
-
6
Synthesizable LPDDR4 Bus Functional Model
- Fully JEDEC spec functionality compliant and reports any non-compliance issues
- Fully cycle accurate model
- Fully synthesizable SystemVerilog/Verilog RTL
-
7
SPI (Serial Peripheral Interface) Flash Verification IP
-
8
Source Code Test Suites AXI Interconnect
-
9
JESD204 Verification IP
- High Performance
- Richly Featured
- Easy to use
-
10
VC Verification IP for SAS
-
11
SRAM Memory Model
-
12
CAN Bus 2.0 Master and Slave UVM Verification IP
- VIP: CAN Bus Master and Slave
- Compliance: ISO 11898 CAN 2.0 Part A & B, CAN FD 1.0
- Language: System Verilog
¹ Top Verification IP Over the Last Two Weeks (Last update: May. 22)
IP Provider: Give the best exposure to your IPs, by listing your products for free in the world's largest Verification IP Catalog