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最新IP
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Bluetooth Low Energy v5.2 IP in TSMC40LP
- Silicon ready design
- Industry leading sensitivity
- Low power consumption
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10-bit SAR ADC TSMC
- Sampling Rate options: 1 MSps;2 MSps;5 MSps;10 MSps;15 MSps;20 MSps
- Quick re-configuration to your specification
- Up to 10-bit resolution
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Ultra-low Jitter Fractional-N Frequency Synthesizer PLL (5nm - 180nm)
- Jitter-Power optimized to meet PCIe1-5 reference clock requirements - replaces 300mW/$2.50 clock chip
- Low area on chip -- keepouts = DRC limit in most cases
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6-bit, 1 GSPS High Performance AFE in 28nm CMOS
- 6-bit resolution, variable update rate up to 1 GSPS
- Fully differential current output, fully specified from -40C to 125C
- Ultra low power dissipation
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Lossless Video Compression (HLVC) Encoder
- True mathematically lossless (bit-exact) compression
- Supports lossless compression of a wide variety of RAW data
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ARC EM22FS safety processor
- Dual-core lockstep safety processor supports ISO 26262 automotive safety standards
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Power Line Communications, PLC, Transceiver, N-PLC, G3-PLC, Prime, IEEE, Sunspec
- Configurable power line communications modem
- Data rates up to 400kbps
- Configurable operational bands (5 - 500 kHz)
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Arm Cortex-M35P
- Improve ML and DSP Performance
- Accelerate Time to Market
- Simplify Software Development
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eFPGA Tile with power management for TSMC 40ULP & 40LP
- Metal Stack: 7 layer metal
- Nominal Supply Voltages (Vj): 1.1 V
- Junction Temperature (°C): −40 to 125
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Lossless Video Compression (HLVC) Decoder
- True mathematically lossless (bit-exact) compression
- Supports lossless compression of a wide variety of RAW data
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12-bit ultra-low power single-ended SAR ADC
- Sample rate from 100kSPS to 1MSPS
- Ultra-low power
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Machine Learning Processor
- Partner Configurable
- Extremely Small Area
- Single Toolchain
热门IP
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1
Machine Learning Processor
- Partner Configurable
- Extremely Small Area
- Single Toolchain
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2
High-performance 64-bit RISC-V architecture multi-core processor with AI vector acceleration engine
- Instruction set: RISC-V RV64GC/RV 64GCV;
- Multi-core: Isomorphic multi-core with 1 to 4 optional clusters. Each cluster can have 1 to 4 optional cores;
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3
56G PAM4 SerDes PHY
- Samsung Foundry 10 nm low-power CMOS
- Supports a maximum LR channel loss of -35dB@14 GHz (ball-toball)
- Supports a maximum -50dB@14 GHz crosstalk
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4
Real-time multi-standard Decoder
- HEVC, H.264, VP9, AVS2 and AV1 Multi format Decoder for UHD (up to 8K) 4:2:0 10bit
- Ideal Solution for Ultra HD Devices.
- Superior Error resilience, concealment, and reporting.
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5
Time Sensitive Networking (TSN) Switched End Node core
- Up to 8 different priority queues, with freely definable VLAN priorities
- Up to 8 phases per cycle according to priority queues
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6
Arm Cortex-M35P
- Improve ML and DSP Performance
- Accelerate Time to Market
- Simplify Software Development
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7
RISC-V 64-bit Processor
- RISC-V 64IMC, with AFDN (ie GCN) to be released
- RISC-V standard PLIC
- RISC-V standard PMP (physical memory protection)
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8
DDR5/4 PHY for Samsung 7LPP
- Supports JEDEC standard DDR5 and DDR4 SDRAMs
- High-performance DDR PHY supporting data rates up to 4800 Mbps
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9
XpressCCIX-AXI Controller IP for PCIe 5.0 with CCIX ESM support
- Controller IP for PCIe 5.0, 4.0, 3.1/3.0 Supporting Root Port, Endpoint, Dual-mode, Switch Port Configurations, with CCIX ESM Support and AMBA AXI Interconect User Interface
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10
PCIe 5.0 IP in Samsung 7nm
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
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11
Transaction-aware embedded cybersecurity solution that can detect, block and record attacks, & prevent propagation
- "Below the operating system" - extra level of security
- Fastest attainable time-to-detection and mitigation
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12
MIPI D-PHY Universal 4 Lane 2.5Gbps
- Supports MIPI Alliance Specification for D-PHY Version 2.1
- Backward compatible with MIPI Specifications for D-PHY v1.2, and v1.1
- Consists of 1 Clock lane and 4 Data lanes
¹ Top Silicon IP Over the Last Two Weeks (Last update: Feb. 23)
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