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最新IP
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Scalable, On-Die Voltage Regulation for High Current Applications
- Enables per-core DVFS
- Localized IR drop mitigation
- Unlocks virtual power islands
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Ultra Compact Ethernet TSN End Station Controller IP for Automotive
- Fully integrated hardware and software solution
- One physical Ethernet port and dedicated host port
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0.6V/10uA, 20uA Bandgap and V2I converter (Voltage to current)
- TSMC MSRF CMOS 55nm
- Dual output reference voltage without trimming 0.6V±3.4%
- Buffered output
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eMMC LDPC Encoder/Decoder
- Supports data rates from 50 MB/s to 9.0 GB/s.
- Enables custom LDPC core development for specific requirements.
- Wide range of codeword sizes.
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AES GCM IP Core
- supports encryption and decryption for modes listed below:
- supports offline and online key schedule
- supports 128, 192 and 256-bit key lengths
- has masked and non-masked modes
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PCIe 6.0 PHY for TSMC N3P
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0, encoding, backchannel initialization
- Supports PCIe Lane Margining at Receiver
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Intra-Panel Multi Strandard TX 8nm
- COG and COF transmitter
- Data Rate : 120M ~ 4.0Gbps
- Supports Power Down and Low-Power modes during V-blank period
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MIPI C-PHY/D-PHY Combo 2-Lane CSI-2 TX+ IP in TSMC 40ULP
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 2 Data lanes in D-PHY mode
- Consists of 2 Data Trio in C-PHY mode
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Camera Scaler IP - DSCALE
- Small Gate Count
- Low Band width
- Optimized for Power Saving
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MIPI DPHY in GF 22FDSOI18 for Automotive
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
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4.5GHz Fractional-N/SSC PLL
- 4nm Low Power Plus (LN04LPP) CMOS device technology
- Dual power supply of 1.2V±10% and 0.85V+5% ~ 0.75V-10%
- Operating junction temperature(Tj): -40°C ~ 125°C
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Kintex Ultra Scale Plus NVMe Host IP
- PCIe RP and EP register configuration is done automatically.
- NVMe register configuration is done automatically.
- Able to manage 8 Name Spaces.
热门IP
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1
40G UCIe PHY IP on Samsung SF4X
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
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2
UCIe Die-to-Die Chiplet Controller
- AXI over UCIe Streaming Protocol
- Link Error Detection and Retry Feature
- APB for Controller Control
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3
PCIe 6.2 Switch
- 1 upstream port, up to 7 downstream ports
- Up to 128 lanes
- Up to x16 link width per port
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4
PVT - Process, Voltage, and Temperature Monitor with Interrupt 7nm/6nm
- ± 4C temperature accuracy without trim
- ± 1C temperature accuracy after single room temperature trim
- Voltage monitor supports both single-ended and differential inputs, with 4:1 input mux
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5
8.5GHz Fractional-N/SSC PLL
- 4nm Low Power Plus (LN04LPP) CMOS device technology
- Dual power supply of 1.2V±10% and 0.85V+5% ~ 0.75V-10%
- Operating junction temperature(TJ): -40°C ~ 125°C
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6
Fractional-N Frequency Synthesizer PLL
- Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
- Input & output frequency ranges greater than 1000:1
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7
TSMC CLN7FF 7nm LPDDR5 PHY - 6400Mbps
- Supports LPDDR5
- DFI 5.1 compliant
- Supports x4, x8 and x16 DRAMs
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8
ARINC 429 IP
- Independent Receivers (Rx) with FIFO
- Independent Transmitter (Tx) with FIFO
- Number of RX and TX line defined by Generics
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9
Compact, low-power, 8bit ADC
- GF 22nm FDX
- High SFDR
- Compact
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10
Standard Cell Library in TSMC (12nm~180nm)
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11
Deskew Frequency Synthesizer PLL
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12
Flipchip 5V Fail-Safe GPIO, 5V GPIO, 5V GPI and I2C Compliant 5V ODIO
- Fail-Safe Architecture
- Two different GPIO footprints.
- I2C Compliant ODIO
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