Audio codec with capacitor-less 106 dB dynamic range ADC and 120 dB SNR DAC with low latency
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最新IP
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Bluetooth 5.4 LE Controller with Link Layer, optional 802.15.4 MAC, early access to Channel Sounding
- Bluetooth SIG Qualified
- Production proven IP, extensively tested, commercially shipping
- Pre-release of Bluetooth Channel Sounding based on draft specification
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32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
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Optimize your 5G NR O-RAN Split 7.2X design with EIC cutting-edge PRACH Design and Verification Suite
- All PRACH formats and configuration indexes described in 3GPP 38.211 are fully supported.
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General Purpose Neural Processing Unit (NPU)
- Hybrid Von Neuman + 2D SIMD matrix architecture
- 64b Instruction word, single instruction issue per clock
- 7-stage, in-order pipeline
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DSC 1.2b Encoder
- Compliant with the VESA DSC 1.2b
- Backward compatible with the VESA DSC 1.1
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12 bit 250MSPS ADC on TSMC 7nm
- TSMC 7nm
- Ultra high-performance low-power ADC
- Integrated input buffer
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DDR5 PHY for Samsung SF4X
- Low latency, small area, low power
- Compatible with JEDEC standard DDR5 SDRAMs up to 8400 Mbps
- Compatible with JEDEC standard DDR4 SDRAMs up to 3200 Mbps
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UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
- 48-Gsps peak sample rate
- 8 bit resolution
- UCIe SP (16x lanes at 16Gbps) with streaming controller
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Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
- Scalable architecture and crypto engines for optimal performance/resource usage
- Configurable for perfect application fit
- 100% CPU offload with low latency and high throughput
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Video Encoder - 4k60 Scalable up to 8K120
- Selectable Video Codecs
- Selectable Bitdepth and Chroma Subsampling Formats
- Scalability through Multi-core Architecture
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Power On Reset (POR)
- Start-Up Reset
- Voltage Monitoring
- Failure Detection
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PCIE Gen7 Controller
- Supports PCIE Gen7 Draft spec.
- FM & NFM modes supported
- 1/2/4/8/16 lane configurable
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3DIO PHY IP for TSMC N5
- Optimized for heterogeneous integration in 3D stacking
- TSMC N5
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NPU IP for Embedded AI
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
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LPDDR5X/5/4X PHY IP in SF5A for Automotive
- Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
- Support for data rates up to 8533 Mbps
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PCIe 7.0 Switch
- Configurable from PCIe 7.0 x8/ PCIe6x16 @1GHz clock down to PCIe 5.0 x1
- Highly scalable with up to 31 configurable external or embedded endpoints
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12-bit, 8 GSPS High Performance Swift™ ADC in 16nm CMOS
- 16nm CMOS
- Ultra high-performance low-power ADC
- 12-bit ADC resolution
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FlexNoC 5 Network-on-Chip (NoC)
- Physical Awareness for faster timing closure
- Higher margins
- Fewer wires
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12-bit 12-Gsps ADC
- 12-Gsps peak sample rate
- 12 bit resolution (10-bit option)
- SMALLER than competing solutions
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Fractional-N Frequency Synthesizer PLL (3nm - 180nm)
- Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
- Input & output frequency ranges greater than 1000:1
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Watchdog Timer
- Watch Dog Timer IP supports- 24-bit prescalar.
- Enable and timeout duration are programmable.
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DDR4 Memory Controller
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Secure-IC's Securyzr™ Fully Digital Physically Unclonable Function (PUF) - PQC Ready
- A worldwide unique PUF IP that does not require any enrollment phase nor a rebuilding phase.
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MCR DDR5 PHY
- Fully pre-assembled design, Drop-in hard macro to ease integration and speed time to market
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