IP搜索

Bluetooth 5.0 LE and Sub-GHz Transceiver

• Sub-GHz bands : Up to request
• Bluetooth 5 TX power: +10 dBm, RX sensitivity: -96 dBm
• Sub-GHz TX power: +20dBm, RX sensitivity: -120 dBm

HDCP 2.3 Transmitter

• Supports HDCP version 2.2 and 2.3 Specifications.
• User keys can be loaded for Authentication.

BFP IQ Compression and De-compression

• Enables lower capacity backhaul like microwave links
• Improves throughput on existing microwave links

AES-GCM Multi-Booster

• High throughput
• Guaranteed performance with small packets
• 128-bit and 256-bit key

10-bit, 2 GSPS High Performance ADC in 28nm CMOS

• Class leading performance
• Ultra low power
• Compact area

Configurable 8-bit 230MS/s or 10-Bit 27MS/s SAR ADC

• TSMC 40nm LP (Low Power Process)
• 1.1V and 1.8V Supplies
• 10 / 8 bit Configurable High-Speed SAR ADC

LPDDR4X and DDR3 multiPHY IP for GF12LP

• Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs

Bluetooth 5.2 Low Energy Baseband Controller, software and profiles

• Compliant with the Bluetooth Low Energy versions 4.2/5/5.1/5.2 specifications
• Supports all mandatory and optional features of Bluetooth low energy

SHA IP Core with native SHA2-256 HMAC support

• FIPS PUB 180-4 compliant SHA2-256 function
• RFC 2104 compliant HMAC mode native support
• SHA2 224 and 256 bit modes support

Gen-Z Switch IP Core

• Full Verilog/SystemVerilog core
• Compliant with the Gen-Z 1.1 Core Specification

Hardware and software platform for contextually aware IoT devices

• Integrated hardware and software platform that aggregates sensing technologies to enable contextually aware IoT devices

MIPI Universal D-PHY IP - MIPI D-PHY v2.5 Specification Compliant

• Supports MIPI Alliance Specification for D-PHY Version 2.5
• Backward compatible with MIPI Specifications for D-PHY v2.1, v1.2, and v1.1

Neural Network Processor for Intelligent Vision, Voice, Natural Language Processing

• Highly efficent neural network inference processor
• Scalable performance from less than 1 TOPS to 100s of TOPS

Deep Learning Processor

• Configurable hardware architecture
• Configurable core number up to three
• Convolution and deconvolution

RISC-V 64-bit Processor

• RISC-V 64IMC, with AFDN (ie GCN) to be released
• RISC-V standard PLIC
• RISC-V standard PMP (physical memory protection)

Deep neural-network accelerator (DNA) AI processor

• Specialized design to take advantage of sparsity in weights and activations for compute and bandwidth reduction

Neuromorphic IP

• Designed for Low-Power Neural Network Processing
• Flexible Training Methods
• Scalable Neuron Fabric

Accelerator for Convolutional Neural Networks

• Include VGG, ResNet, MobileNet, and other custom use cases.

Die-to-Die PHY IP in TSMC N7

• Offers leading performance, power, and area / beachfront per terabit
• Includes 16 lanes of NRZ and PAM-4 transmitters or receivers

Low-Latency 10/100/1000 Ethernet MAC

• Supports IEEE 802.3
• Enables high-precision syn-chronization in TSN networks

MIPI ASPMI Slave

• Compliant with 1.3 Apple MIPI SPMI Specification
• Full MIPI SPMI Slave functionality

DesignWare CXL Controller IP

• Fully supports the CXL 1.0 and 1.1 specifications
• Supports PCI Express 5.0 mode with 32 GT/s and x16 link width

100M/1G/2.5G/5G/10G Managed Ethernet Switch

• Full-duplex 100M/1G/2.5G/5G/10G Ethernet Interfaces
• Configurable from 3 up-to 32 Ethernet ports

CAN Bus Controller with Message Filter (Mailbox concept)