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最新IP
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Xilinx Ultra Scale Plus SATA HOST IP
- Compliant with Serial ATA III specification and signaling rate is 6Gbs
- Xilinx Ultra Scale Plus GTHE4 FPGA
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14-Bit 1.7MHz Bandwidth Continuous Time Sigma Delta ADC
- TSMC 40nm ULP Process
- 1.1V & 1.8V Supplies
- Continuous-Time Sigma-Delta ADC
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MIPI C-PHY/D-PHY Combo IP Universal, 4.5Gsps/4.5Gbps in TSMC 22ULP
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v1.2
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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H.265/HEVC / H.264/AVC Multi-Codec Hardware IP
- Image size: Up to 8K（8192×4320） 60fps
- HEVC/AVC Multi-Codec
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MIPI-I3C Master/Slave
- Compliance as per MIPI-I3C Basic v1.0.
- Backward compatibility with I2C.
- Two wire serial interface up to 12.5MHz using Push-Pull.
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Wide Range PLL - TSMC N5
- TSMC 5nm CLN5
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Multi-Protocol 32G PHY IP for GF 12LP
- Supports 1.25 to 32 Gbps data-rate
- Supports PCI Express 5.0, 1G to 400G Ethernet, CCIX, and SATA protocols
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Line Driver Differential Current Amplifier IAMP 100MHz
- 28nm TSMC HPC+ Process, 0.9V/2.5V,
- Differential Current Input and Output
- Programmable Current Gain from -3dB up to
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Power Management Unit - iHP SiGe BiCMOS 0.25 um
- iHP SG25H5_EPIC SiGe BiCMOS 0.25 um
- Bandgap voltage source 1.08V
- Low drop out voltage regulator
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GF22FDX Low Power PLL
- Lowest power in the industry 0.5mW - 1.5mW
- Smallest area in the industry
- Customizable in weeks
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High-performance 32-bit RISC CPU
- 32-bit RISC architecture
- 16 or 32 general purpose registers
- 104 basic instructions and 10 addressing modes
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MIPI D-PHY 2 Lane CSI2-TX 1.2G
- TowerJazz 65nm
- Consists of 1 Clock lane and up to 2 Data lanes
- Supports MIPI Standard 1.2 for D-PHY
热门IP
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1
Highest performance real-time processor
- The highest performance real-time processor – double the total performance of Cortex-R7.
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2
4K/8K Scalable Multi-Format Video Decoding IP Core
- Prefectly suited for 8K video resolutions
- Selectable video codecs
- Low latency decoding
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3
PUF-based Secure Crypto Co-processor
- Provide a much easier to adopt hardware RoT with less vulnerability
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4
eFPGA IP cores for GF 12LP/12LP+ Rad Hard By Design
- Globalfoundries 12LP/12LP+
- Rad Hard By Design
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IEEE 802.11a/b/g/n/ac/ax 40MHz 2.4/5GHz Wi-Fi IP in TSMC40LP
- Complete 2.4/5 GHz low-power Wi-Fi solution
- Designed for TSMC 40nm LP CMOS process
- Internal power amplifiers
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USB 3.1 Type-C PHY IP for TSMC 5FF
- Supports 10 Gbps and 5 Gbps data rates
- x1 and x2 configurations (USB 3.1 PHY only)
- Low active and standby power
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FTP Non Volatile Memory for Standard TSMC 40nm ULP
- Ultra Low Power Read (30uA/MHz for 39b-IO) at 0.85V Single Power
- 10-Time Programmable
- > 10 years retention
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12-bit 160MS/s Dual Channel IQ ADC on GLOBALFOUNDRIES 22nm FDX
- GF 22nm FDX Process
- 0.8V and 1.6V Supplies
- 12-bit Dual-Channel High-Speed SAR ADC
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DDR5/4 Controller IP with a CHI Interface
- Complete, integrated DDR solution from a single vendor when combined with Synopsys’ DesignWare DDR PHY IP
- Supports DDR5 and DDR4 memory protocol based SDRAMs and U/SO/R/LRDIMMs
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64-bit RISC-V microcontroller. Small core for 64-bit applications.
- Architecture: RV64IMCAFNB
- Machine and User modes
- 2-3-stage pipeline
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Low-power, 16-bit RISC CPU with cache
- 16-bit RISC architecture
- 16 or 32 general purpose registers
- 92 basic instructions and 10 addressing modes
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FlexCAN Controller for CAN 2.0 with CAN-FD
- Full implementation of CAN FD and CAN 2.0 B
- Compliant with ISO 11898-1
- Flexible mailboxes configurable
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