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HBM2/2E PHY - High Performancce, Low Power and Low Latency Design in a Small Area
- Data Rate 0.5-3.2Gbps per I/O
- Self-Refresh Feature included
- Channel Density Up to 32Gbits
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Ultra low power temperature sensor for X-FAB 350nm
- Silicon proven in X-FAB XH035
- Input Voltage: 2.0 – 3.3V
- Power consumption: 80µW typical
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DDR5/4 PHY IP for TSMC N7
- Supports JEDEC standard DDR5 and DDR4 SDRAMs
- High-performance DDR PHY supporting data rates up to 4800 Mbps
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Low Drop 50mA Regulator
- 12nm TSMC FFC Process, 7 Metals Used
- (No Analog Options) with Deep-Nwell
- 2.0V- 2.2V Input Voltage
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Ethernet PCS 10G/25G
- User controlled AutoNegotiation (IEEE 802.3 Clause 37) with full programmability
- Support for 10G Energy-Efficient Ethernet (EEE) compliant with the IEEE, 802.3az specification
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D2D Controller IP (Die-to-Die Interface)
- Ultra-high-bandwidth and performance (For e.g. 1024-bit AXI interface at 2GHz can provide up to 2 Tbps)
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Wide band 3.5 GHz -7 GHz low noise PLL synthesizer
- TSMC CMOS 55 nm
- Output frequency range from 3.5 MHz to 7 GHz
- Reference frequency range from 5 MHz to 50 MHz
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CXL 2.0 Dual Mode Controller
- Compatible with CXL 2.0 specification and backward compatible with CXL V1.0 and CXL V1.1
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Turnkey TWS Bluetooth Audio platform
- Compliant with Bluetooth 5.2
- Turnkey hardware and software solution, reducing integration complexity and effort
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CXL 2.0 Integrity and Data Encryption (IDE) Security IP
- Compliant with the CXL 2.0 IDE specifications for CXL.cache/mem
- Compliant with PCI Express IDE specification for CXL.io
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5.5 Volt Comparator with Programmable Thresholds on TSMC 40nm
- 40nm TSMC ULP eFlash Process, 6 Metals Used
- (No Analog Options)
- 1.1V, 2.5V and 3.3V or 5V Power Supplies
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Dual-Core HEVC, AV1 & H.264, AVS2, VP9 Combined Decoder
- HEVC/H.265 Main Profile @L5.1
- AVC/H.264 BP/CBP/MP/HP Profile @L5.2
- AV1 Main Profile @L5.1
热门IP
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Ka-Band beamforming and transceiver ASIC platform
- Ka-Band operation: Rx 17.7 to 21.2 GHz, Tx 27.5 to 30 GHz
- Ka-Band fine gain control in each Rx/Tx element
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112G Ethernet PHY IP in TSMC N5
- Supports full-duplex 9.9 to 112Gbps data rates, Enabling 100G, 200G, 400G, 800G Ethernet interconnects for wired network infrastructure
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Asynchronous Network on Chip IP
- High performance interconnects, Ultra-low-latency and Deep pipelining
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DDR5/LPDDR5 PHY-Speed up to 6400Mb/s and Low IO pin count
- Fully compliant with DDR5 / LPDDR5 / DDR4 / LPDDR4 / DDR3 / LPDDR3 / DDR2 / LPDDR2 / DDR JEDEC SDRAM standards
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Ethernet MAC & PCS 10G/25G
- Deficit Idle Count for maximum data throughput
- Comprehensive statistics gathering
- Supports VLAN and jumbo frames as an option
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32G Multi-protocol SerDes PHY
- Multi-protocol PHYs supporting data rate in the range of 2.5 Gbps – 32 Gbps
- Available in GLOBALFOUNDRIES 22FDX® process node
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12-bit 80MS/s Dual-Channel IQ ultra-low power SAR ADC
- UMC 22nm ULP Process
- 0.8V and 1.8V Supplies
- 12-bit Dual-Channel High-Speed SAR ADC
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MIPI CSI-2 Receiver
- Realize MIPI I/F with Low cost
- Series development for small quantity, large variety
- Available for evaluation of Product development
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General Purpose PLL for VIS 150nm
- Wide range N, M, P integer dividers.
- 40MHz – 600MHz output frequency range.
- Comparable frequency range 8MHz – 50MHz.
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AXI4 to/from AXI4-Stream Scatter-Gather DMA
- AXI4 Memory Mapped to Stream & Stream to Memory Mapped DMA
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10-bit SAR ADC TSMC
- Sampling Rate options: 1 MSps;2 MSps;5 MSps;10 MSps;15 MSps;20 MSps
- Quick re-configuration to your specification
- Up to 10-bit resolution
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IEEE 1588v2 PTP SW & HW
- Delivers Performance
- Highly Configurable
- Silicon Agnostic
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