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I3C Host Controller v1.2

• Compliant with MIPI I3C Specification v1.2
• Compliant with MIPI I3C HCI Specification v1.1
• Supports up to 12.5 MHz operation using Push-Pull

AV1/HEVC/AVC/VP9 Video Decoder HW IP 8K30fps@500MHz

• High-quality encoding
• Improved bandwidth efficiency
• Low delay encoding

MIPI C-PHY v2.0 D-PHY v2.1 RX for TSMC N6

• Compliant with the MIPI D-PHY specification, v2.1
• 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
• Compliant with the MIPI C-PHY specification, v2.0

Safety Enhanced General Purpose Neural Processing Unit (NPU)

• Hybrid Von Neuman + 2D SIMD matrix architecture
• 64b Instruction word, single instruction issue per clock
• 7-stage, in-order pipeline

Logic based Hardware Root-of-Trust - Physical Unclonable Function (PUF)

• Secure provisioning
• Secured identities
• High entropy seeds

On-Die PDN Analyzer for Transistor-Level Visibility and Telemetry

• Transistor-level PDN visibility
• PDN telemetry and onboard analytics across the silicon lifecycle

10G Base T Ethernet PHY

• CAD Proven database
• Ready to go for fabrication and characterization
• ASIC volume production ( in future)

LPDDR5X/5/4X PHY IP on TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps

Audio Sample Rate Converter

• Studio-Grade Audio Quality
• Scalable and Efficient
• Fast Synchronization

Lightweight Root-of-Trust

• Rapidly implement secure boot and attestation capabilities without significant area, cost, or complexity overhead.
• Prevent malicious software attacks, unauthorized access, and firmware tampering to safeguard critical device functionality.

2kx8 Bits OTP (One-Time Programmable) IP, TSM- 40ULP 1.1/2.5V Process

• Small IP size
• Low program voltage/current
• Low read voltage/current

Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)

• Ultra Low Standby Current
• .72V to .88V
• Internal Bist Mux

TSMC GF LVDS Tx/Rx with optional CMOS I/O

UMC 40nm LP/RVT Logic Process SYNS-like 9T ECO_M1 Cell Library

802.11a and 802.16a OFDM FFT Core

MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)

• Compliant to MIPI for C-PHY specification Version 1.2
• Compliant to MIPI for D-PHY specification Version 1.2

Nano power DC-DC converter in GF 22FDX with ultra-low quiescent current and high efficiency at light load

• Ultra-low quiescent current (300 nA) to ensure minimum current consumption in deep sleep / hibernation mode

TSMC 3nm (N3E) 1.2V/1.8V GPIO Libraries

TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries

JTAG 2-Wire to 4-Wire Adapter

• IEEE 1149.1 and IEEE 1147.7 compatible.
• Small logic overhead.
• Clock frequencies to 25MHz.

NVMe Target IP Core

MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N5, N3E, N3P)

40nm Low Leakage VHS, Channel Length 40nm, RVT Logic Process Standard cell Library

IEEE 802.11ah MAC/PHY

• 1 MHz and 2 MHz channel width
• S1G_1M, S1G_SHORT PPDU
• Mandatory MAC including TXOP, RID, SST, TWT, AID,…, RAW