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最新IP
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MIPI DSI-2 Transmitter Interface IP
- DSI-2 operates in continuous clock behaviour in clock lane when implemented in D-PHY physical layer.
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Advanced DPA- and FIA-resistant FortiMac HMAC SHA2 IP core
- Ultra-strong side-channel attack protection (at least 1B traces)
- Protected against fault injection attacks including SIFA
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Ultra low-power Microphone, Audio, IoT interface
- Complete ultra low-power microphone/audio/IoT interface + ADC
- 140uW interface + 200uW ADC power
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USB Power Delivery 3.1 Physical Layer
- Fully characterized
- USB compliance
- In mass production
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PCIe 6.0 Controller IP with AMBA bridge
- Supports all required features of the PCI Express 6.0, 5.0, 4.0, 3.1, 2.1, and 1.1 specifications
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Fractional-N PLL for Performance Computing in TMSC 16FFC
- Fractional multiplication with frequency up to 4GHz
- Low jitter (< 10 ps RMS)
- Small size (< 0.004 sq mm)
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USB 3.2 Gen2x2 with PIPE 4.3 and USB2.0 with UTMI+ interface
- Fully compliant USB 3.2 Gen2x2 with PIPE 4.3 and USB2.0 with UTMI+ interface
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32-bit High Performance RV32GC Single/Multicore RISC System-on-Chip
- High Performance 32-bit RV32GC CPU
- Proprietary 6-stage pipeline
- Single or multicore implementation
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KYBER-512/768/1024 KEM - Balanced Post-Quantum Key Encapsulation IP Core
- Small Resource Requirements
- Fast Performance
- Secure Architecture
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TSMC CLN7FF 7nm LPDDR5 PHY - 6400Mbps
- Supports LPDDR5
- DFI 5.1 compliant
- Supports x4, x8 and x16 DRAMs
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LPDDR5X/5/4X Controller for Automotive
- Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
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USB-C Interface
- USB Power Delivery 3.1-certified
- VCONN Management, including over-current protections
热门IP
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64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
- 64-bit in-order dual-issue 8-stage CPU core with up to 1024-bit Vector Processing Unit (VPU)
- Symmetric multiprocessing up to 8 cores
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Compact, Secure and Performance Efficiency 32-bit RISC-V Core
- AndeStar™ V5/V5e Instruction Set Architecture (ISA)
- Andes extensions for performance and code size enhancements
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3
2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- Efficiency
- Composability
- Programmability
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4
Universal Chiplet Interconnect Express (UCIe) PHY and Controller
- Package Flexibility
- Power Efficiency
- Low Latency
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LPDDR5X, LPDDR5, LPDDR4X, LPDDR4, LPDDR3 PHY and Controller
- Low Latency
- Low Power and Area
- Reliable
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Advanced I2C/SMBus Controller and Target Device
- Supports I2C v7.0, SMBus v3.2, PMBus v1.2
- Configurable APB2, APB3 and APB4 programming interface
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PUF-based Hardware Root of Trust
- PUF-based Unique ID
- PUF-based True Random Number Generator
- PUF-based Secure Key Storage
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Ramping 12-bit ADC with Sequencer
- TSMC180 process
- Small Area: 0.21mm^2
- -40 to 125 Deg C
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9
Automotive MIPI A-PHY Sink IP (2-Lane)
- Compliant with MIPI A-PHY specification version 1.0
- Support Gear-2 up to 4Gbps
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10
IEEE 802.1 Clause 4 MAC
- Full CSMA/CD compliance, including half and full-duplex
- Support for 10 and 100 Mb/s operation
- Single MAC address filtering
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11
ARC software-based hardware safety mechanism for EM Functional Safety processor
- ARC STL implements a hardware safety mechanism for ARC FS Processors using software driven testing approach
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Ray tracing GPU
- High-quality gaming and visuals
- Better battery life
- Smoother performance
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