IP搜索

1.8V Fault Tolerant General Purpose I/O Staggered Pad Set

• Ultra low leakage
• Multi-Voltage (1.2V, 1.5V, 1.8V)
• LVCMOS / LVTTL input with selectable hysteresis

Camera capture unit for multi-camera systems

• Down-scaling
• De-interlacing
• Histogram measurement

1-32Gbps PCI-Express Gen1 - Gen5 PHY

• Receive Equalization
• Power Optimization
• Configurability

800G Multi-rate Ethernet aggregator

• Combines Ethernet streams at a variety of rates to a single multi-channel interface at the MAC

32-bit Multiprocessor with Level-2 Cache-Coherent

• Symmetric multiprocessing up to 4 cores
• Level-2 cache and cache coherence support
• AndeStar™ V5 Instruction Set Architecture (ISA).

USB 3.1 PHY IP for Samsung 11LPP

• Supports 10 Gbps and 5 Gbps data rates
• x1 and x2 configurations (USB 3.1 PHY only)
• Low active and standby power

12-bit 6MS/s ADC in TSMC 28nm HPC+

• TSMC 28nm HPC+ Process
• 0.9V and 2.5V Supplies
• 12-bit SAR ADC

LPDDR4X PHY

• Samsung 14nm
• Supports 4.266Gbps LPDDR4
• Off-chip driver (OCD)

Power Quencher® Capless LDO

• Input Power Supply: 2.5 to 6.0 V
• Output Voltage: 1.2 to 5.5 V (adjustable)
• Maximum Load Current: 300 mA

USB3.0/PCIe2.0 Combo PHY in TSMC28HPC+

• Compliant with USB3.0 and PCIe2.0 base specification
• Standard PHY interface (PIPE) enalbes multiple IP sources for PCI2/USB3 MAC layer

5G-NR LDPC Decoder

• High throughput
• Low-power and low-complexity design
• Block-to-block on-the-fly configuration

MIPI DSI Master PHY in Samsung 28FDSOI

• Supports MIPI Specification for D-PHY Version 2.1
• Consists of 1 Clock lane and 4 Data lanes
• Supports both high speed and low-power modes

Neuromorphic IP

• Designed for Low-Power Neural Network Processing
• Flexible Training Methods
• Scalable Neuron Fabric

Machine Learning Processor

• Outstanding Performance
• Highly Efficient
• Optimized Desig

1-32Gbps PCI-Express Gen1 - Gen5 PHY

• Receive Equalization
• Power Optimization
• Configurability

H.264/AVC, H.265/HEVC, VP9 and JPEG Encoder

• State of the art video encoding quality
• Unique multi-format and scalable architecture
• Scalable video resolution up to 8K resolution, support for multi-stream encoding

Generic Polar FEC Codec

• Fully customizable to any standard or new waveform
• Blocklength up to 1024 bits
• Throughput up to 100 Gbits/s

MIPI D-PHY 4 Lane CSI2-TX 1.2G

• Consists of 1 Clock lane and up to 4 Data lanes
• Supports MIPI Standard 1.2 for D-PHY
• Supports both high speed and low-power modes

Gigabit Ethernet PHY

• Integrated 10/100/1000Mbps Transceiver
• Compliant with IEEE 802.3, IEEE 802.3u, and IEEE 802.3ab

Dual-CORE HEVC+H.264 combined codec for 8Kp60

• HEVC - Main/Main 10 Profile, Level 5.2 High-tier
• H.264 - High/High 10 Profile, Level 6.0

Low Voltage Detector

• Samsung Foundry 14nm Low Power Plus (LN14LPP) CMOS 1.1 to 1.95V, 0.8V dual power supply

10-bit, 12-bit, 14-bit, Low Speed SAR ADC in TSMC (180nm, 90nm, 65nm, 55nm, 40nm, 28nm, 16nm, 12nm)

Deep neural-network accelerator (DNA) AI processor

• Specialized design to take advantage of sparsity in weights and activations for compute and bandwidth reduction

Camera SLVS-EC/sub-LVDS combo Receiver 2.5Gbps 8/12-Lane

• SLVS-EC / MIPI CSI compliant