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1 – 33Gbps Die-to-Die SerDes PHY

• 1 - 33 Gbps continuous operation
• 1 mW/Gbps
• World’s best area and latency in segment

MIPI STP Master

• Compliant with MIPI STP Specification version 2.0 and 2.2.
• Supports STP interface.
• Supports ATB interface.

DVB-GSE Ethernet Tunnel Core

• GSE encapsulation of Ethernet frames
• Designed for high throughput and low latency

64X1 Bits OTP, GF22nm FDX 0.8V/1.8

• Fully compatible with standard GF22nm FDX process
• Low read power: <1uW at 0.4V supply voltage

Power Quencher® Capless LDO

• Silicon-proven 40 nm
• 1 mA
• excellent quiescent current for IoT

12-bit, 20Msps Data Converter

• TSMC 16FFC
• 20Msps
• 12-bit

Low Drop Out 5mA Regulator in TSMC 180nm

• TSMC 180nm High Voltage Mixed-Signal Process, 6 Metals Used
• 4V – 15V Input Voltage
• 1.8V +/-4% Output Voltage

Display Processor for VR

• Superior User Experiences on Mobile
• Efficiency and Bandwidth Savings
• Increased Performance, Same Footprint

Tensilica Vision Q7 DSP

• Doubles Vision and AI Performance for Automotive, AR/VR, Mobile and Surveillance Markets

HBM2 PHY for Samsung 10LPP

• Lowest latency for data-intensive applications
• Memory controller interface uses DFI 4.0-like standard

Sony Camera LVDS Interface

• Compatible with all Sony® FCB-EV Series LVDS video cameras
• Support for HD1080p60 (double-mode)
• Support for HD1080p30 (single-mode)

4K x 8 Bits OTP, GF22nm FDX 0.8V/1.8

• Fully compatible with GF22nm FDX CMOS core logic process
• Low voltage: 0.8V+/-10% read and 1.2V+/-100mv program

Accelerator for Convolutional Neural Networks

• Include VGG, ResNet, MobileNet, and other custom use cases.

True Random Number Generator (TRNG) Digital Noise Source based on a robust fully-digital entropy source

• ​Robust, low-footprint, standard-cell based entropy source
• Entropy generation through thermal noise extraction

SHA-256 encryption and decryption coprocessor

• ​compliant with the FIPS 180-4 standard
• full support of SHA-256 and SHA-224 hash functions

AV1, VP9, H.265/HEVC, H.264/AVC and JPEG Encoder

• State of the art video encoding quality
• Unique true multi-format and scalable architecture
• Flexible, user configurable software

112G LR Multi-protocol SerDes PHY in 7nm FINFET

• Supports up to 4 duplex lanes and data rates from 10.3 to 106 Gbps

Cognitive Radio IP Core

• Parameterisable Input bit width
• Parameterisable FFT size
• Parameterisable HMM window length

MIPI CSI-2 Master PHY for GlobalFoundries 22FDX

• Consists of 1 Clock lane and up to 4 Data lanes
• Supports MIPI Alliance Specification for D-PHY Version 2.1

ITS-G5/802.11p PHY/MAC

• SoC architecture
• Robust receiver including advanced Doppler signal processing
• Scalable solution
• On demand customization available

Fractional-N Frequency Synthesizer PLL (5nm - 180nm)

• 1MHz up to 1.6GHz input frequency range
• 1MHz up to 3.6GHz output frequency range
• 24 bit fractional resolution

50mA Regulator

• 0.18um TSMC eLL Process, 6 Metals Used
• 3.0V Input Voltage
• 1.8V Output Voltage +-3%

2-32GBPS Multi-Protocol SerDes Transceiver

LPDDR4/3/2 DDR4/3/2 ComboPHY