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Ultra Wide Band Digital Up Converter (DUC)

• Ultra High Sample RateOutput (>3GSamp/s)
• Parametrized Sample Per Cycle (SPC)
• Change SPC throughout core

USB 3.1 PHY (10G/5G) in Samsung 8LPP Process

• Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes

12-bit 2MS/s ADC

• TSMC 55nm ULP Embedded-Flash
• No Analog Options
• 2.5V and 1.2V Supplies

1-112Gbps Long-Reach (LR) Multi-Standard-Serdes (MSS)

• High speed A/D
• Sub-sampling clock multiplier
• Master controller

Hardware RTP Stack for H.264 Stream Decapsulation

• RTP Decapsulation for H.264 NAL Streams
• Easier Integration For Faster Development

Low Power Clock Multiplier PLL for 40nm TSMC ULP CMOS

• Wide range M, P, and N integer dividers.
• 40MHz – 600MHz output frequency range.
• Input frequency range 1.4MHz – 32MHz.

8-Channel Comparator with Programmable Thresholds

• 90nm TSMC Logic LP Process, 6 Metals Used
• 1.2V and 3.3V Power Supplies
• 8-Bit Voltage DAC resolution

Dual-channel Programmable CT ΔƩ I/Q AD converter

• 5 GSPS Internal Sampling Rate
• 20-300 MHz Full Performance Bandwidths
• 2.0Vpp Full Scale Range

Ultra Compact 32-bit RISC-V CPU Core

• AndeStar™ V5/V5e Instruction Set Architecture (ISA)
• Compliant to RISC-V technology
• Support RV32IMAC/EMAC

10M/100M/1G/2.5G Ethernet TSN MAC

• Delivers Performance
• Highly Configurable
• Feature Rich
• Silicon Agnostic

Safe and Secure CAN bus IP

• Bosch CAN protocol compliant, DO254 DAL A Certifiable
• Real-time Cyber Resilience IDS/IPS Features
• Monitor CAN Bus Circuit Failures During Active Transmission

Enhanced Security Package option for ARC HS cores

• Two privilege levels and MPU-based access control
• Data and instruction path integrity checking to prevent fault injection attacks

Deep Learning Processor

• Configurable hardware architecture
• Configurable core number up to three
• Convolution and deconvolution

NB-IOT Transceiver RF Front-end

• -110 dBm Rx Sensitivity
• <3 dB Noise Figure
• +100 dB Rx Gain

32 Gbps Multi-protocol SerDes PHY

• Multi-protocol PHYs supporting data rate in the range of 2.5 Gbps – 32 Gbps
• Available in GLOBALFOUNDRIES 22FDX® process node

MIPI D-PHY / C-PHY Combo IP for TSMC 22nm

• Compliant to MIPI Alliance Standard for C-PHY specification Version 1.2
• Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2

Safe and Secure CAN bus IP

• Bosch CAN protocol compliant, DO254 DAL A Certifiable
• Real-time Cyber Resilience IDS/IPS Features
• Monitor CAN Bus Circuit Failures During Active Transmission

Dual 12-bit 2-GS/s Analog Front-End in 28nm

• TSMC 28nm HPC+
• Dual 12-bit 2GS/s ADC
• Dual 12-bit 2GS/s DAC

LPDDR5/4/4X PHY for TSMC N7

• Lowest latency for data-intensive applications
• Highest data rates with detailed system guidelines

Ultra Compact 32-bit RISC-V CPU Core

• AndeStar™ V5/V5e Instruction Set Architecture (ISA)
• Compliant to RISC-V technology
• Support RV32IMAC/EMAC

24-bit Sigma Delta Stereo Audio DAC in TSMC 28nm

• 24-bit stereo audio DAC
• Audio interface is serial i2s
• Sampling frequency 48KHz

Power-on-Reset and Supply Monitoring

• TSMC 40nm Logic LP Process
• Power-on Reset output
• Early Warning output

TSMC CLN20SOC 20nm Clock Generator PLL - 700MHz-3500MHz

MIPI® CSI-2 Slave D-PHY

• Consists of 1 Clock lane and 4 Data lanes.
• Supports MIPI Alliance Specification for D-PHY Version 2.1
• Supports both high speed and low-power modes.