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DVB-RCS2 Multi-Carrier Receiver

• Compliant with ETSI EN 301 545-2 (DVB-RCS2)
• Support for Linear Modulation Bursts of Table A-1
• Optional support for Spread-spectrum

AXI4 Memory-Mapped to/from AXI4-Stream DMA

• Independent AXI4 compliant single channel modules
• AXI4-Lite port for access to control and status registers

28 nm Bulk CMOS IP - V- & E-band mmWave components

• Bulk CMOS
• 0.9 V supply
• Silicon-proven in 28 nm CMOS

Power Management Unit (1.1 - 1.4V output voltage, load current 5 mA)

• TSMC CMOS 55 nm
• Output voltage: 1.1 ... 1.4 V
• Low current consumption

Multichannel module supporting ARINC429 Receiver/Transmitter

• Multichannel module supporting ARINC429 Receiver/Transmitter.
• Configurable module supporting any number of receivers and transmitters

PHY IP for PCIe 6.0 in TSMC N5

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 6.0, encoding, backchannel initialization
• Supports PCIe Lane Margining at Receiver

Generic Waveform Generator

• Scalable approach
• Huge set of supported protocols
• Variable set of driver ans stimuli units possible

IP cores for Edge AI in XR devices

• Ultra-fast Response Time
• Zero-latency Switching
• Low Power

Charge Pump with ULP Ludicrous Mode on GF 22FDSOI

• Fast response Charge Pump
• Output current up to 100mA
• Ludicrous Low Power Mode

Ultra-Low Phase Noise Digital LC PLL

• Wideband integrated jitter <400fs in integer mode, <800fs in fractional mode with high-speed / clean reference with active fractional noise cancellation

AV1/HEVC/AVC Dual-core Video IP

• High-quality encoding
• Bandwidth efficiency
• Low delay encoding

Automotive-Grade MIPI DSI-2 Controller IP

• Complete single-vendor solution for mobile and mobile-influenced applications
• Proven MIPI CSI-2, DSI and I3C controllers
• Silicon-proven D-PHY and M-PHY

UCIe Controller

• Low Latency controller for UCIe-based die-to-die connectivity
• Includes Die-to-Die Adapter layer and Protocol layer

32-bit RISC-V processor specifically designed for the Automotive and Functional Safety markets

• 32-bit RISC-V ISA
• ASIL B and ASIL D area optimised product variants
• Functional Safety Package and Independent Assessment

PCIe 5.0 PHY

• Advanced, built-in diagnostics including on-chip digital RX eye scope
• Internal/external loopback
• 8b/10b and 128b/130b encoding and decoding

UCIe PHY IP for TSMC N5

• Data rates up to 16Gbps per pin
• Self-contained hard macro
• Self-calibrating and training

RISC-V 64-bit Standard CPU

• Efficient Out of Order Superscalar w/ hardware-multithreading
• High Performance Vector Processing Unit (Optional)

High performance and low latency hardware accelerated zram/zswap at unmatched power efficiency

• Compression ratio: 2-4x across diverse data sets
• Compression throughput: 8GB/s
• Decompression throughput: 10.5GB/s

TSMC based IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes

Fully Digital Physically Unclonable Function (PUF)

Universal Chiplet Interconnect Express (UCIe) PHY and Controller

• Package Flexibility
• Power Efficiency
• Low Latency

12-bit SAR ADC TSMC

Bi-Directional LVDS with LVCMOS

Ultra-Low Phase Noise Digital LC PLL

• Wideband integrated jitter <400fs in integer mode, <800fs in fractional mode with high-speed / clean reference with active fractional noise cancellation