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I3C Host Controller v1.2

• Compliant with MIPI I3C Specification v1.2
• Compliant with MIPI I3C HCI Specification v1.1
• Supports up to 12.5 MHz operation using Push-Pull

AV1/HEVC/AVC/VP9 Video Decoder HW IP 8K30fps@500MHz

• High-quality encoding
• Improved bandwidth efficiency
• Low delay encoding

MIPI C-PHY v2.0 D-PHY v2.1 RX for TSMC N6

• Compliant with the MIPI D-PHY specification, v2.1
• 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
• Compliant with the MIPI C-PHY specification, v2.0

Safety Enhanced General Purpose Neural Processing Unit (NPU)

• Hybrid Von Neuman + 2D SIMD matrix architecture
• 64b Instruction word, single instruction issue per clock
• 7-stage, in-order pipeline

Logic based Hardware Root-of-Trust - Physical Unclonable Function (PUF)

• Secure provisioning
• Secured identities
• High entropy seeds

On-Die PDN Analyzer for Transistor-Level Visibility and Telemetry

• Transistor-level PDN visibility
• PDN telemetry and onboard analytics across the silicon lifecycle

10G Base T Ethernet PHY

• CAD Proven database
• Ready to go for fabrication and characterization
• ASIC volume production ( in future)

LPDDR5X/5/4X PHY IP on TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps

Audio Sample Rate Converter

• Studio-Grade Audio Quality
• Scalable and Efficient
• Fast Synchronization

Lightweight Root-of-Trust

• Rapidly implement secure boot and attestation capabilities without significant area, cost, or complexity overhead.
• Prevent malicious software attacks, unauthorized access, and firmware tampering to safeguard critical device functionality.

2kx8 Bits OTP (One-Time Programmable) IP, TSM- 40ULP 1.1/2.5V Process

• Small IP size
• Low program voltage/current
• Low read voltage/current

Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)

• Ultra Low Standby Current
• .72V to .88V
• Internal Bist Mux

4K Video Scaler IP Core

• Technology independent soft IP Core for FPGA, SoC and ASIC devices
• Supplied as human readable VHDL source code (or Verilog on request)

ONFI 4.0 NAND Flash PHY upto 800Mbps

• ONFI 1/2/3/4/5 compliant;
• Toggle/Toggle2 mode;
• Maximum 2400Mbps; (PHY_CLK = 1200Mhz)

ONFI 5.1 3,600MT/s PHY, 28nm, 12nm and 7nm

JESD204D Transmitter and Receiver IP

• Designed according to JEDEC JESD204D Standard.
• Supports up to 24 lanes per IP cores.

7-bit, 64 GSPS ADC Ultra Low Power

• Ultra-high bandwidth time-interleaved ADC
• 7-bit ADC resolution
• Sampling rate up to 64GSPS

JESD204D - Succesfully Taped out, Silicon Agnostic IP core

Wi-Fi 6 (ax)+BLEv5.4+15.4 Dual Band RF IP for High-End Applications.

NPU IP for Embedded AI

• Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code

SGMII PHY

JESD204D

VESA DSC V1.2 Decoder

Scalable Ultra-High Throughput Image Scaler

• Standalone Scaling Operation
• Advanced Scaling Implementation
• Easy Implementation and Verification