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AES-GCM Ultra-Low Latency
- High throughput: 64 GB/s (512 Gbps)
- Ultra-low latency
- Optional CRC support for data integrity
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16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
- Support PCIe G1 to G4 with PCS soft-macro supporting PIPE 4.4.1
- Support xPON applications: Sym/Asym GPON, Sym/Asym 10GPON, Sym EPON, Sym/Asym 10GEPON
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Embedded flash IP, 1.5V/5V 130nm
- G1 is cost effective embedded flash IP to support from medium density to 100KBytes
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CCSDS 231.0 LDPC Encoder and Decoder
- Support for code rate 1/2
- Uncoded block sizes of 64 and 256 bits
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MIPI C-PHY/D-PHY Combo IP DSI RX in TSMC22ULP
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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12-bit 160MS/s ultra-low power DAC
- 22nm TSMC ULL Process,
- 1.8V and 0.8V Supplies
- Sampling Rate up to 160MS/s
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HDCP 2.3 Embedded Security Modules on DisplayPort 2.0/1.4
- Fully compliant with HDCP 2.3 specification
- Certified Transmitter/Receiver/Repeater solutions for HDMI and DisplayPort interfaces
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25 to 1750 MHz quadrature mixer
- TSMC CMOS 55 nm
- Operating frequency range from 25 to 1750 MHz
- Noise figure 8.2 dB
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PCIE 5.0 PHY in Samsung 10/8LPP, SMIC 14SFE/SF+, and TSMC 12FFC
- Support 32Gbps serial data transmission rate
- Utilizes 8-bit, 16-bit or 32-bit parallel interface to transmit and receive data
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SERDES IP 16Gbps per channel
- 8 channel SERDES (TXRX), operating at data rates from 1.5Gbps to 16Gbps per channel
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FPGA Evaluation Platform
- For Codasip Application Processor RISC-V cores
- Including AXI or AHB interconnect and PeripheralsAXI or AHB interconnect
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AI accelerator - 4.5K, 9K, or 18K INT8 MACs
- Performance efficient 18 TOPS/Watt
- Scalable performance from 18K MACS
- Capable of processing HD images on chip
热门IP
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AI accelerator - 2.25K, 4.5K, or 9K INT8 MACs
- Performance efficient 18 TOPS/Watt
- Scalable performance from 2-9K MACS
- Capable of processing HD images on chip
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FPGA Evaluation Platforms for RISC-V Processor Cores
- Greatly simplifies the evaluation of a Codasip embedded RISC-V core by providing a ready-to-go platform including common peripherals, Xilinx memory and software examples.
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Gigabit Ethernet PHY
- Comply with IEEE 802.3ab, 802.3u, and 802.3
- Support IEEE 802.3az Energy Efficient Ethernet
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Ethernet Subsystem 10G/25G
- Flexible
- 5G Ready
- Ease-to-use and Reliable
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PCIe Controller for USB4 Hosts and Devices, supporting PCIe Tunneling
- Designed to the USB4 Specification v1.0
- Follows PCIe 1.0 protocol, but can operate at any compatible speed
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Automotive MIPI A-PHY Source IP - 1-Lane
- Compliant with MIPI A-PHY specification version 1.0
- Support Gear-2 up to 4Gbps
- Support data bus width: 20-bit parallel interface
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Asynchronous Network on Chip IP
- High performance interconnects, Ultra-low-latency and Deep pipelining
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Complete Neural Processor for Edge AI
- Designed for Low-Power Neural Network Processing
- Flexible Training Methods
- Scalable Neuron Fabric
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5G/802.11ax MIMO Analog Front-End on TSMC 12nm FFC
- TSMC 12nm FFC Process,
- Customizable AFE
- 1.8V and 0.9V Supplies
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32G Multi-protocol SerDes PHY
- Multi-protocol PHYs supporting data rate in the range of 2.5 Gbps – 32 Gbps
- Available in GLOBALFOUNDRIES 22FDX® process node
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Viterbi Decoder
- Hard or soft decoder with configurable soft bit widths
- Parameterisable generator polynomials
- Parameterisable code Constraint length
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Powerline (PLC), Wireline, G.hn, G,Fast, Analog Front-End (AFE) ultra-efficient Area and Power
- High Performance.
- Low Power
- Low Area
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