New Silicon IP
-
Memory Compiler in TSMC(16nm,22nm,28nm,40nm,55nm,90BCD+,110nm,152nm,180BCD)
-
HHGrace 0.11um LP Multiple Power Supply IO library
-
Zero Additional Mask MTP IP, 2.2-5V 4kbit Towerjazz 180 PM
- Supports high temperature and long retention life time for severe automotive requirement.
-
Zero Additional Mask MTP IP, 2.2-5V 4kbit HHGrace 180BCD
- High Temperature Operation
- Large Program Size enables Short Testing Time
- Low Cost
-
High ESD analog IO library
- Analog Pads
- Power Pads
- Ground Pads
-
ESD solution set for LV & advanced processes
-
600MHz General Purpose Clock Multiplier PLL for 180n CMOS
- Wide range N, M, P integer dividers.
- 40MHz – 600MHz output frequency range.
- Compare frequency range 8MHz – 75MHz.
-
Zero Additional Mask MTP
- Up to 1kB densities
- Up to 100k P/E cycles
- No additional mask required
-
OSC - HHGrace 110nm ULL
- High accuracy and low coefficient of temperature
- High PSRR
IP Provider: Give the best exposure to your IPs, by listing your products for free in the world's largest Silicon IP catalog (8,000 products from more than 400 companies)