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DO-254 Ready MIL-STD-1553 A/B compliant IP with DDC software API and register compatibility

JPEG Extended Encoder

Master I3C bus controller with FIFO

IEEE 802.11ah MAC/PHY

• 1 MHz and 2 MHz channel width
• S1G_1M, S1G_SHORT PPDU
• Mandatory MAC including TXOP, RID, SST, TWT, AID,…, RAW

Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component

• Flexible and independent clocks for control-plane and reference clock
• Up to 32 outputs, each in their own clock domain

Deep captureDebug IP for Intel FPGA

• Configurable upstream link, up to 4 transceivers at 12.5 Gbps each.
• Downstream link to configure IP triggers and data group

Many-Channel Centralized DMA Controller with AMBA AXI Interconnect

• Up to 2048 DMA channels, extensible upon request
• Up to 512 Virtual Machines, extensible upon request
• AMBA AXI4 interfaces with 256-bit data path

DPDK-aware FPGA/GPP data mover

• Line rate agnostic: Operates at any line rate, including 1/5/10/25/40/50/100/400 GbE
• Up to 150 Gbps and 120 Mpps with a contemporary PCIe Gen3x16 interface, Gen4 Ready

Video Tracking FPGA IP core for Xilinx and Altera

• Tracking up to 80 fps at core clock frequency 300 MHz and object size of 128x128 pixels.
• The IP core implements 1 tracking channel. If sever-al channels are required, several cores need to be used.

Video Tracking FPGA IP core for Xilinx and Altera

• Tracking up to 80 fps at core clock frequency 300 MHz and object size of 128x128 pixels

MIPI CSI-2 Receiver

• 1 to 4 data lanes
• Number of data lanes can be configured statically at synthesis time and dynamically during run-time

LEON3FT Fault-tolerant processor

• Register file SEU error-correction of up to 4 errors per 32-bit word
• Cache memory error-correction of up to 4 errors per tag or 32-bit word