New Silicon IP
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Blockchain Hardware Accelerator
- Wide variety of ECC curves supported (Weierstrass, Edwards, Montgomery, Twisted-Edwards, …)
- Ideal for FPGA/ASIC integration
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IEEE 802.11i MAC
- SoC architecture
- Scalable solution
- On demand customization available
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Crypto Coprocessor
- Scalable architecture and crypto engines for optimal performance/resource usage
- Configurable for perfect application fit
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ARIA Crypto Engine
- Supports a wide selection of programmable ciphering modes
- Supports encryption & decryption
- Supports 128-bit, 192-bit & 256-bit key sizes
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PGA IP core T-COR-32 is designed to solve the problems of targeting and targeting. The IP core is used in unmanned aerial vehicles, combat modules, fire control systems, fire control systems and target designation systems.
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Video Tracking FPGA IP core for Xilinx and Altera
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JPEG Extended Encoder
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Master I3C bus controller with FIFO
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TLS Handshake Hardware Accelerator
- RSA, ECC and more
- > 1 GHz in 16nm
- 400-500 MHz on mid-range/high-end FPGA
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