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New Silicon IP
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PGA IP core T-COR-32 is designed to solve the problems of targeting and targeting. The IP core is used in unmanned aerial vehicles, combat modules, fire control systems, fire control systems and target designation systems.
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Video Tracking FPGA IP core for Xilinx and Altera
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I2C Bus Interface - Master with FIFO
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QSPI FLASH Controller with Execute in place – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support)
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PCIe 5.0, 4.0, 3.1/3.0 Multi-Host Switch IP Core with NTB Supporting up to 32 Hosts, 32 Devices
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Deep Learning Processor
- Configurable hardware architecture
- Configurable core number up to three
- Convolution and deconvolution
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NVMe Host Recorder on Mini-ITX Zynq 7
- Higher performance
- Simple to use
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JPEG dual channel encoder
- Baseline JPEG compliant (ITU T.81), Motion JPEG
- Up to 12 bits depth possible (default: 8 bit)
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DO-254 Ready MIL-STD-1553 A/B compliant IP with DDC software API and register compatibility
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DVB-CSA Descrambler
- Drop-in module for Spartan™-6, Virtex™-6, Artix™-7, Kintex™-7, Virtex™-7 FPGAs and Zynq™
- DVB/ATSC compliant
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JPEG Extended Encoder
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Advanced Encryption Standard Module
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