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Blockchain Hardware Accelerator

• Wide variety of ECC curves supported (Weierstrass, Edwards, Montgomery, Twisted-Edwards, …)
• Ideal for FPGA/ASIC integration

IEEE 802.11i MAC

• SoC architecture
• Scalable solution
• On demand customization available

Crypto Coprocessor

• Scalable architecture and crypto engines for optimal performance/resource usage
• Configurable for perfect application fit

ARIA Crypto Engine

• Supports a wide selection of programmable ciphering modes
• Supports encryption & decryption
• Supports 128-bit, 192-bit & 256-bit key sizes

PGA IP core T-COR-32 is designed to solve the problems of targeting and targeting. The IP core is used in unmanned aerial vehicles, combat modules, fire control systems, fire control systems and target designation systems.

Video Tracking FPGA IP core for Xilinx and Altera

I2C Bus Interface - Master with FIFO

QSPI FLASH Controller with Execute in place – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support)

PCIe 5.0, 4.0, 3.1/3.0 Multi-Host Switch IP Core with NTB Supporting up to 32 Hosts, 32 Devices

Deep Learning Processor

• Configurable hardware architecture
• Configurable core number up to three
• Convolution and deconvolution

NVMe Host Recorder on Mini-ITX Zynq 7

• Higher performance
• Simple to use

JPEG dual channel encoder

• Baseline JPEG compliant (ITU T.81), Motion JPEG
• Up to 12 bits depth possible (default: 8 bit)