Search IP on Xilinx

Scalable UHD JPEG 2000 Encoder - 8 up to 16 bits per Component Lossy or Numerically Lossless Image / Video Compression

• ISO/IEC 15444-1 Compliant and Standalone Operation
• Advanced JPEG 2000 Implementation
• Easy Implementation and Verification
• Trouble-Free Technology Map and Implementation

RivieraWaves Bluetooth 5.2 dual mode Baseband Controller

Video Codec IP using RAW input­ (CFA)

• Low complexity for ASIC & FPGA
• No external DDR (optional)
• Extreme low latency

Deterministic Random Bit Generator (DRBG)

• NIST 800-90A/B/C compliant
• Health test
• AES-CTR based (CTR_DRBG)

Blockchain Hardware Accelerator

• Wide variety of ECC curves supported (Weierstrass, Edwards, Montgomery, Twisted-Edwards, …)
• Ideal for FPGA/ASIC integration

IEEE 802.11i MAC

• SoC architecture
• Scalable solution
• On demand customization available

Crypto Coprocessor

• Scalable architecture and crypto engines for optimal performance/resource usage
• Configurable for perfect application fit

ARIA Crypto Engine

• Supports a wide selection of programmable ciphering modes
• Supports encryption & decryption
• Supports 128-bit, 192-bit & 256-bit key sizes

PGA IP core T-COR-32 is designed to solve the problems of targeting and targeting. The IP core is used in unmanned aerial vehicles, combat modules, fire control systems, fire control systems and target designation systems.

Video Tracking FPGA IP core for Xilinx and Altera

I2C Bus Interface - Master with FIFO

QSPI FLASH Controller with Execute in place – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support)