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New Silicon IP
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Deep Learning Processor
- Configurable hardware architecture
- Configurable core number up to three
- Convolution and deconvolution
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NVMe Host Recorder on Mini-ITX Zynq 7
- Higher performance
- Simple to use
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JPEG dual channel encoder
- Baseline JPEG compliant (ITU T.81), Motion JPEG
- Up to 12 bits depth possible (default: 8 bit)
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DO-254 Ready MIL-STD-1553 A/B compliant IP with DDC software API and register compatibility
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DVB-CSA Descrambler
- Drop-in module for Spartan™-6, Virtex™-6, Artix™-7, Kintex™-7, Virtex™-7 FPGAs and Zynq™
- DVB/ATSC compliant
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JPEG Extended Encoder
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