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I2C Bus Interface - Master with FIFO

QSPI FLASH Controller with Execute in place – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support)

JPEG dual channel encoder

• Baseline JPEG compliant (ITU T.81), Motion JPEG
• Up to 12 bits depth possible (default: 8 bit)

DO-254 Ready MIL-STD-1553 A/B compliant IP with DDC software API and register compatibility

Master I3C bus controller with FIFO

Video Frame Buffer

Serial RapidIO 2.1 Endpoint IP Core

Platform Manager Utility Function Core IP

PCS Pipe IP Core

PCI Express x1, x4 Root Complex Lite IP Core

Median Filter

LPDDR SDRAM Controller