New Silicon IP
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Scalable UHD JPEG 2000 Encoder - 8 up to 16 bits per Component Lossy or Numerically Lossless Image / Video Compression
- ISO/IEC 15444-1 Compliant and Standalone Operation
- Advanced JPEG 2000 Implementation
- Easy Implementation and Verification
- Trouble-Free Technology Map and Implementation
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Deterministic Random Bit Generator (DRBG)
- NIST 800-90A/B/C compliant
- Health test
- AES-CTR based (CTR_DRBG)
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Blockchain Hardware Accelerator
- Wide variety of ECC curves supported (Weierstrass, Edwards, Montgomery, Twisted-Edwards, …)
- Ideal for FPGA/ASIC integration
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I2C Bus Interface - Master with FIFO
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QSPI FLASH Controller with Execute in place – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support)
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JPEG dual channel encoder
- Baseline JPEG compliant (ITU T.81), Motion JPEG
- Up to 12 bits depth possible (default: 8 bit)
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DO-254 Ready MIL-STD-1553 A/B compliant IP with DDC software API and register compatibility
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Master I3C bus controller with FIFO
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TLS Handshake Hardware Accelerator
- RSA, ECC and more
- > 1 GHz in 16nm
- 400-500 MHz on mid-range/high-end FPGA
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In-line bus protection module
- On-the-fly encryption/decryption and authentication
- Transparent for the processor
- Scalable data bus width (32, 64, 128 bits)
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Video Frame Buffer
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Serial RapidIO 2.1 Endpoint IP Core
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