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Synopsys 56G Ethernet PHY IP in 12FFC

Maestro Adaptive Workload Manager [PLL] actively adapts to workload changes to boost silicon performance

• Fully SCAN enabled
• Fully customizable to each application
• Wide operating voltages available for DVFS

Maestro Clock Generation Module [PLL], 10x smaller than existing solutions

Maestro Clock Generation Module [PLL], 10x smaller than existing solutions

100MSa/s 6-Bit DAC

• TSMC: 12/16nm CMOS FinFET
• Resolution: 6-bit
• Sampling rate: 100MSa/s

200MSa/s 8-Bit DAC

• TSMC: 12/16nm CMOS FinFET
• Resolution: 8-bit
• Sampling rate: 200MSa/s

PHY IP for PCIe 5.0 on TSMC N7

• Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, and PIPE specifications
• x1, x2, x4, x8, x16 lane configurations with bifurcation

Nano power Real Time Clock (RTC) with 32kHz oscillator

• TCXO with third order polynomial compensation
• Less than 25ppm freq. error between -20ºC and 85ºC

MIPI C-PHY Combo PHY & Controller (support combo TTL, LVDS, HiSPI)

MIPI D-PHY/C-PHY Combo PHY & Controller (support combo TTL, LVDS, HiSPI)

112Gbps ELR SerDes IP for TSMC 5nm

112Gbps ELR SerDes IP for TSMC 7nm and 6nm