Process Detector (For DVFS and monitoring process variation)
PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
SMS5000 does not require any external Loop filter capacitor(s) for clock Synthesis PLL or Clock recovery circuitry making it immune to PCB related noise typically encountered, and provides a completely integrated solution.
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Block Diagram of the PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
PCI-Express PIPE PHY Transceiver IP
- 1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
- USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC
- USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in SMIC 14SF+
- USB 3.2 Gen2 PHY IP, Silicon Proven in UMC 28HPC
- USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in TSMC 28HPC+
- PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P)