The PCIe2.0 PHY IP is a customizable physical layer (PHY) IP solution for Consumer Electronics. The PHY IP integrates mixed signal circuits to enable both 2.5GT/s and 5.0GT/s data transfer speeds while conforming to the PCIe2.0 basic standards. The PCIe2.0 PHY IP is made up of two layers: the Physical Media Attachment (PMA) layer and the Physical Coding Sublayer (PCS), and it simply links to either the PCIe2.0 MAC layer using the standard PIPE-3.0 interface.
The PCIe2.0 PHY IP transceiver is designed for low power consumption and small device area while maintaining good performance and data throughput. The PCIe2.0 PHY IP includes an on-chip physical transceiver solution with ESD protection, a built-in self-test module with inbuilt jitter injection, and a dynamic equalization circuit that assures full support for high-performance architectures.