Multi Protocol Switch IP Core for Safe and Secure Ethernet Network
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PCIe 4.0 Serdes PHY IP 芯片在 TSMC 7nm 中得到验证
这个PCIe 4.0 PHY IP设计符合PCIe 4.0规范的要求，兼容PIPE 4.4.1接口规范，以低功耗、多通道和高性能为设计目标，支持各种高带宽的传输应用场景。这个PCIe 4.0 PHY IP设计符合PCIe 4.0规范的要求，兼容PIPE 4.4.1接口规范。这个PCIe 4.0 SerDes PHY IP核的数据传输速率可达16Gbps，并兼容PCIe 3.1、PCIe 2.1和PCIe 1.1规范等旧版本所规定的2.5Gbps、5.0Gbps和8.0Gbps速率。PCIe 4.0 IP可以满足各种信道情况下的需要，同时支持TX和RX均衡化方法.
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Block Diagram of the PCIe 4.0 Serdes PHY IP 芯片在 TSMC 7nm 中得到验证
PCIe IP Core IP
- PCIe 5.0 Integrity and Data Encryption Security Module
- PCIe 6.1 Controller
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP