1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
PCIe 3.0 Serdes PHY IP,在 SMIC 28SF 中经过硅验证
T2M提供了顶尖的、高度可配置的PCIe 3.0 PHY,符合ECN 1.0a和PCIe 3.0规范,并针对客户和企业应用程序进行客制化设计。这个PHY IP的支持8通道,能扩大吞吐量,同时支持广泛的应用程序。客户可选择使用客户端版本为更低的数据速率(Gen2)或更少的通道进行定制。此外,它还提供了L1 substates L1.1和L1.2,能够以较小的尺寸集成到具有严格功率要求的应用程序中.
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PCIe 3.0 IP
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- 1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY