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PCIe 2.0 Serdes PHY IP, Silicon Proven in UMC 40LP
The PCIe2.0 PHY IP transceiver is optimized for low power consumption and small die area while retaining great result and data throughput. The PCIe2.0 PHY IP includes an on-chip physical transceiver solution with ESD protection, a built-in self-test module with inbuilt jitter injection, and a dynamic normalization circuit that ensures full support for high-performance configurations.
The PCIe2.0 PHY IP is a customizable physical layer (PHY) IP solution for Consumer Electronics. The PHY IP integrates mixed signal circuits to enable both 2.5GT/s and 5.0GT/s data transfer speeds while conforming to the PCIe2.0 basic standards. The PCIe2.0 PHY IP is made up of two layers: the Physical Media Attachment (PMA) layer and the Physical Coding Sublayer (PCS), and it simply links to either the PCIe2.0 MAC layer using the standard PIPE-3.0 interface.
The PCIe2.0 PHY IP is a customizable physical layer (PHY) IP solution for Consumer Electronics. The PHY IP integrates mixed signal circuits to enable both 2.5GT/s and 5.0GT/s data transfer speeds while conforming to the PCIe2.0 basic standards. The PCIe2.0 PHY IP is made up of two layers: the Physical Media Attachment (PMA) layer and the Physical Coding Sublayer (PCS), and it simply links to either the PCIe2.0 MAC layer using the standard PIPE-3.0 interface.
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Block Diagram of the PCIe 2.0 Serdes PHY IP, Silicon Proven in UMC 40LP
pcie3.0ip IP
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