Scalable multicore architecture for a range of macrocells, small cells, cloud-RAN, DFE/DPD/ and more
POR 4.0 PHY SMIC14SF+
查看 POR 4.0 PHY SMIC14SF+ 详细介绍:
- 查看 POR 4.0 PHY SMIC14SF+ 完整数据手册
- 联系 POR 4.0 PHY SMIC14SF+ 供应商
PCIE 3.0 PHY IP
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 4.0 PHY IP with 16GT/s optimized for low power consumption (Silicon Proven in TSMC 28HPC+)
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 5.0 SerDes PHY