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Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP
Version 1.4 of the DisplayPort transmitter PHY is capable of transmitting data at rates of 1.62Gbps (RBR) to 5.4Gbps (HBR2). programmable analogue features, a built-in equaliser, 100-ohm termination resistors, common-mode biassing of the CDR bandwidth, the regulator voltage, the BGR voltage, and the terminator resistance Support 1.8V/0.9V power supplies for PLL testing and internal analogue signal monitoring.
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Block Diagram of the Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP
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