DDR4/3/LPDDR3 Combo PHY & Controller
Note that all INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. DDRn bus width can be from 4 bit to 72 bit or more. INNOSILICON is happy to pre-assemble each PHY for our customer so that integration becomes extremely easy.
The combo PHY solution includes DDRn controller and PHY, supporting DDR4/3/LPDDR3. With configurable timing and driving strength parameters to interface to the wide variety of SDRAMs, the PHY is very flexible with advanced command capability to increase SDRAM operation efficiency.
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PHY IP
- ONFI 5.0 PHY
- USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- TSMC CLN4P 4nm DDR5 PHY - 6400Mbps
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect