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2 port IP Listing

1747 IP Cores (241 - 280)

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HDCP 2.3 Embedded Security Modules on DisplayPort/USB Type-C

The Synopsys Embedded Security Modules (ESMs) for High- Bandwidth Digital Content Protection 2.3 (HDCP 2.3) are complete solutions that provide designers with a robust, standards-compliant implementation ...

241
Embedded Security Modules for HDCP 2.3 on HDMI IP

The Synopsys Embedded Security Modules (ESMs) for High- Bandwidth Digital Content Protection 2.3 (HDCP 2.3) are complete solutions that provide designers with a robust, standards-compliant implementation ...

242
200G and 400G Ethernet PCS IP

The Synopsys Ethernet 400G and 200G Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802.3bs standard and provides a complete set of features that enable users to define an optimized ...

243
High-Density eMRAM Compiler TSMC 22ULL

The Synopsys Foundation IP optimized for the TSMC’s 22nm Ultra Low Leakage (ULL) process provides designers an extensive offering of high-speed, high-density, ultra-high density, and eMRAM ...

244
Single port SRAM Compiler - low power retention mode and column repair

Single Port SRAM Compiler with Low Power Retention Mode and Ultra Low Leakage

245
Two port register file (1R1W) with low power retention mode

Low Leakage. Mobile Semiconductor's Bulk 22 ULL Register file memory compiler generates dual port Register File instances using the Bulk 22ULL process. Each ultra-low leakage memory instance ...

246
Single Port SRAM with low power retention mode, high speed pins on 1 side

Low Leakage. Mobile Semiconductor's Bulk 22 ULL SRAM memory compiler generates memory instances using the Bulk 22ULL process. Each ultra-low leakage memory instance primarily uses low leakage ...

247
Single Port, High Speed, Multi Bank SRAM Memory Compiler

Low Leakage. Mobile Semiconductor's SP-HSB-GF22FDX-PLUS memory compiler generates high speed memories by splitting memory into 1 to 4 banks for reduced bit line length and enhanced timing ...

248
Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)

Mobile Semiconductor's RF1P-ULL-GF22FDX-PLUS memory compiler generates Dual Port Register File instances using the GLOBALFOUNDRIES 22nm FDX-PLUS CMOS process.

249
Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)

Low Leakage. Mobile Semiconductor's RF1P-ULL-GF22FDX-PLUS memory compiler generates Dual Port Register File instances using the GLOBALFOUNDRIES 22nm FDX-PLUS CMOS process.

250
CAN 2.0, CAN FD & CAN-XL 总线控制器

实现了一个CAN总线控制器，该控制器根据CAN 2.0，CAN FD和CAN XL规范执行串行通信。它支持最初的Bosch协议和ISO 11898中定义的和ISO规范（包括ISO 19898-4中定义的时间触发操作（T...

5 Testimonials
Srivi Dhruvanarayan, Vice President of Hardware, SiMa.ai

251
Tessent RISC-V 追踪和调试

Tessent UltraSight-V 是 Tessent 嵌入式分析产品系列的一部分，是基于 RISC-V 的 SoC 的全面解决方案。UltraSight-V 结合了嵌入式 IP 和软件，使嵌入式软件工程师能够更加高效地...

252
支持CXL.io，CXL.cache，CXL.mem 的 Compute Express Link（CXL）规范的控制器IP

XpressLINK™是可参数化的Compute Express Link（CXL）控制器软件IP，专为ASIC和FPGA实现而设计。 XpressLINK控制器IP为CXL.io路径应用了PLDA已硅验证的PCIe 5.0 XpressRICH控制器...

253
根据CXL Link规范设计的CXL控制器IP，具备针对SoC实现而优化的AMBA接口

XpressLINK-SOC™是可参数化的Compute Express Link（CXL）控制器软IP，专为ASIC和FPGA实现而设计。 XpressLINK-SOC控制器IP为CXL.io路径在PLDA PCIe 5.0 控制器IP基础上(基于PLDA...

254
Single port SRAM Compiler - low power retention mode

Silicon proven, qualified and in high volume production. Single Port compiler offers the lowest retention power on the market.

255
PCIe 5.0,4.0,3.1 / 3.0根端口，端点，双模，具有Native用户界面的交换机端口Controller IP核

XpressRICH5是一款可配置且可扩展的PCIe Controller软 IP，专为ASIC和FPGA实现而设计。 XpressRICH5 IP符合PCI Express 5.0,4.0和3.1 / 3.0规范，以及PCI Express（PIPE）规范的P...

2 Testimonials
June Paik, CEO, Furiosa

256
HDMI 2.0 Tx PHY 和控制器 IP，在 TSMC 12FFC 中经过硅验证

HDMI发送器（TX）IP产品符合HDMI 2.0和1.4标准，为各种设计实现提供了必要的组件。这些IP解决方案针对功率和面积进行了优化，已在硅上进行了验证，包括可配置的数字控制器和高速混...

257
H.264 High Profiles Encoder - High 10, High 4:2:2 and High 4:4:4 (12 bit 4:2:2 or 4:2:0) Profiles

The H264-HP-E core from Alma Technologies is an advanced ITU-T H.264 High profiles hardware encoder. It supports real time encoding of 4:2:0 and 4:2:2 video streams, in 8-, 10- or 12-bit per ...

258
CEVA-RivieraWaves UWB turnkey MAC and PHY platform IP

CEVA-RivieraWaves UWB is a low power ultra-wideband (UWB) MAC and PHY platform IP based on 802.15.4 HRP and the FiRa Consortium requirements. It delivers secure, cent...

259
DisplayPort TX IP for high-bandwidth applications (12nm, 16nm, 28nm)

M31 DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort TX supports 20Gbps UHBR20, 13.5Gbps UHBR13.5, 10Gbps ...

260
USB 2.0 OTG 高/全/低速双重角色 IP 内核

我们公司提供高度可配置和适应性强的USB 2.0 OTG控制器IP核，适用于广泛的应用。该控制器符合最新的行业标准（USB 2.0和USB OTG），并在主机模式下与现有的Windows、Linux和Androi...

261
USB 2.0 nanoPHY in SMIC (65nm)

The Synopsys USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low-power mobile and consumer applications such as feature-rich smartphones, digital ...

262
PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P)

The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. The PHY’s ...

263
PCIe 4.0,3.1 / 3.0根端口，端点，双模式，具有Native用户界面的交换机端口Controller IP核

XpressRICH4是一款可配置且可扩展的PCIe controller Soft IP，专为ASIC和FPGA实现而设计。 XpressRICH4 IP符合PCI Express 4.0和3.1 / 3.0规范，以及PCI Express（PIPE）规范的PH...

264
CAN 2.0B Bus Controller IP Core

The Controller Area Network (CAN) controller IP that implements the CAN2.0A, CAN2.0B as well as newer high performance Non ISO CAN-FD protocols. It can be integrated into devices that require ...

265
ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm

The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP Core is changing in accordance with it. New applications are emerging and innovative IP solutions are needed to keep ...

266
32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter

This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7, 15 or 31 order, up to 32Gbps. Error count is accurate: no double counts or omissions regardless of error sequence or frequency ...

267
32Gbps, 7/15 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter

This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7 or 15 order, up to 32Gbps. Error count is accurate: no double counts or omissions regardless of error sequence or frequency ...

268
32Gbps, 31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter

This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps. Error count is accurate: no double counts or omissions regardless of error sequence or frequency of ...

269
95 dB of SNR, 24-bit audio CODEC with headphone output and line-out

SoC integrators targeting portable audio applications such as Smart Phones, PMP, PDA should demonstrate optimal recording performances as well as the best sound quality, while starring the longest ...

270
Display Port v1.4 Rx PHY 和控制器 IP，在 TSMC 40LP 中经过硅验证

这个 DP 1.4 Rx IP每个数据通道的传输速率高达5.4 bps（HBR2），交付件包含可编程模拟参数，如CDR带宽、均衡器强度、终端电阻和BGR电压。此外，还提供了可测试性选项，如PLL单独测...

271
Display Port v1.4 Tx PHY 和控制器 IP，在 UMC 40SP 中经过硅验证

1.4版本的DisplayPort Tx PHY IP支持1.62Gbps（RBR）到5.4Gbps（HBR2）之间的数据速率。这个设计包含具有可编程模拟功能的内置均衡器、100欧姆终端电阻以及共模偏压CDR带宽、调节...

272
Display Port v1.4 Rx PHY 和控制器 IP，在 UMC 40SP 中经过硅验证

这个 DP 1.4 Rx IP每个数据通道的传输速率高达5.4 bps（HBR2），交付件包含可编程模拟参数，如CDR带宽、均衡器强度、终端电阻和BGR电压。此外，还提供了可测试性选项，如PLL单独测...

273
Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in IDM 180nm /150nm)

Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR Bandwidth, Equalizer strength, Terminator resistor, BGR voltage ...

274
LVDS/FPD 链路 IP，在 GF 28LPe 中经过硅验证

这个用于LVDS发射器的物理层IP，由20车道（4 x 4D1C）LVDS接收器组成，并支持高达1.5Gbps的数据速率。这个IP在LVDS模式下，串行数据和并行数据都被组织成4个通道，每个通道7位宽。...

275
LVDS Rx IP，在 GF 28LPe 中经过硅验证

这个用于LVDS接收器的物理层IP，由20车道（4 x 4D1C）LVDS接收器组成，并支持高达1.5Gbps的数据速率。这个IP的输入时钟为25MHz到150MHz，其序列化器高度集成功能完善，不需要添加...

276
Display Port v1.4 Tx PHY 和控制器 IP，在 TSMC 40LP 中经过硅验证

1.4版本的DisplayPort Tx PHY IP支持1.62Gbps（RBR）到5.4Gbps（HBR2）之间的数据速率。这个设计包含具有可编程模拟功能的内置均衡器、100欧姆终端电阻以及共模偏压CDR带宽、调节...

277
FlexNoC 功能安全( FuSa) Option 帮助满足应对随机硬件故障的 ISO 26262 ASIL B 和 D 要求。

最新一代 FlexNoC 5 互连及其集成的兼顾物理感知技术为布局和布线团队提供了更好的起点，同时减少了互连面积和功耗。与手动物理迭代相比，FlexNoC 5 的周转时间缩短了 5 倍。FlexN...

278
Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process.

Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process.

279
UMC 40nm Low Power Process , Two Port Register File with dual power rail

UMC 40nm Low Power Process , Two Port Register File with dual power rail

280

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