PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N5, N4P, N3E, N3P)
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200G and 400G Ethernet PCS IP
The Synopsys Ethernet 400G and 200G Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802.3bs standard and provides a complete set of features that enable users to define an optimized PCS in products across a range of 400G/200G Ethernet applications. The Synopsys PCS IP is designed to work with Synopsys Ethernet MAC IP to deliver solutions for 200G & 400G Ethernet applications. The multi-channel, multirate PCS allows flexible use of the various lanes for different PMA interfaces. The IP also includes multiplexed Reed-Solomon Forward Error Correction (RS-FEC) functions for use by different channels at various speeds
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