The CL12611IP Transmitter converts 24bits LVCMOS parallel data into 3-channnel sub-LVDS serial data streams. A Phase-locked transmit clock is transmitter in parallel with the data streams. The CL12611IP transmitter is programmed for rising edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 85MHz, 24bits data are transmitted at a rate of 680Mbps per sub-LVDS data channel. The CL12611IP Transmitter is an ideal means to solve EMI and cable size problems associated with wide, high speed CMOS interface.
- Input Clock: 20MHz to 85MHz shift clock support
- Output Clock: 80MHz~340MHz
- Output Data Rate: 160Mbps~680Mbps
- Low power single 1.2V or 1.8V or 2.8/3.3V (Option: 1.0/1.2/1.8V Logic/Level Shifter)
- Clock Edge Programmable
- Narrow bus reduces cable size
- PLL requires no external components
- ±150mV swing sub-LVDS for low EMI
- sub-LVDS DDR format
- This specification is Sony 12-bit CIS Parallel Interface specification.
- This IP is used in Mobile-Phone and DSC products.
- This IP is used in ISP products.
- Our sub-LVDS technology is very small consumption current.
- We uninvested form VC and other company now, so our IP can be very cheep.
- Our ASIC partner is GUC, PGC, Faraday, GSI.
- We can make Custom-IP used this IP.
- We are supplying circuits-macro for other IP license. And the customer can make hard-macro from circuits-macro.
- GDSII data
- SPICE netlist for LVS
- Timing models
- LEF file
- Verilog model
- Final simulation result
- Layout layer map file
- LVS and DRC log files
- Circuits data
- Simulation enviloment files
- IBIS or Hspice netlist file