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1 Gbps LVDS Transmitter
The interface to the core logic includes signal pin (INP) to transmit data and control pin ( EN) to configure the state of the transmitter. There are other two internal pins (VREF and BP_TX, BPC_TX, BN_TX) to get voltage reference and to gets voltage reference from transmitter bias. OUTP and OUTN are complementary outputs to connect to the bonding pads. LVDS transceiver cell may be used for half-duplex data transmission.
The LVDS transmitter is designed on iHP SiGe BiCMOS 0.13 um technology.
The LVDS transmitter is designed on iHP SiGe BiCMOS 0.13 um technology.
特色
- iHP SiGe BiCMOS 0.13 um
- 3.3 V power supply
- 1 Gbps (DDR MODE) switching rates
- Conforms to TIA/EIA-644 LVDS standards
- Optimized for pad-limited layout design
- Temperature range: -40 °C to + 85 °C
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
可交付内容
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
应用
- Point-to-point data transmission
- Multidrop buses
- Clock distribution
- Backplane data transmission
- Cable data transmission
- Half-duplex or duplex data transmission
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