V-Trans 's LVDS technology solutions eliminate the trade-offs in speed, low power, low noise (EMI), and BOM cost saving for high performance data transmission applications.
This LVDS transmitter is partially terminated to offer the best trade-off between signal integrity and power saving.
This library use In-line I/O pitch of 75um.
(40um I/O pitch is also available, please contact us)
- • 1P6M layout structure based on 0.18um 1P6M 1.8V
- generic logic process.
- • 3.3V/1.8V ±10% supply voltage, -40/+125°C temperature.
- • IEEE Standard 1596.3-1996 and ANSI/TIA/EIA- 644-A Specifications.
- • Up to 1250Mb/s DDR, or 800Mhz clock.
- • RSDS support (reduced swing capability)
- • Power down mode.
- • CMOS output for chip testability (JTAG…)
- • Bandgap reference I/O cell included
- • Small area : [contact us]
- • Comes with a set of ESD protected power pads, corner, filler and break cells for easy integration.
- • Silicon proven, and test report available.
- Block Diagram:
- - low cost solution
- - very easy to integrate
- - full support
- The library includes:
- - a partial source terminated LVDS transmitter,
- - a set of filler cells, power cells and corner cell,
- - reference voltage cell (bandgap) / external reference
- - GDSII
- - LVS netlist
- - LIB timing
- - LEF abstract
- - Verilog/VHDL model
- - Datasheet
- - Application Note