The LVDS I/O is a three-module design (input, output and reference block). The LDP_OU_450_18V_T is a 1400MBit/s LVDS Driver, LDP_IN_450_18V_DN is a 1400MBit/s LVDS Receiver and the LDP_RE_000_18V is the voltage reference and current bias for up to 16 drivers. The LDP_OU_450_18V_T is designed to drive either 50Ω or 100Ω differential termination. This cell has been designed to meet the standard SubLVDS specifications (SMIA 1.0 Part 2:CCP2). Currently there is no standard for 50Ω termination
Using this SubLVDS Pad Set, the system can achieve very high data rates per pin with simple termination requirements and low EMI. The driver has been optimized for speed/power and can be ported to various pure digital CMOS processes from 0.18μm down to 28nm technologies. The LDP_OU_450_18V_T has been optimized for 1400MBit/s operations. The receiver has been designed with no hysteresis in order to optimize sensitivity and skew.
The driver design has all the necessary components for transmit of SubLVDS data and a temperature stable internal reference for setting of the SubLVDS signaling voltage and common mode level. This provides user flexibility in deploying multiple SubLVDS transmitters. The reference block is required for the SubLVDS drivers to provide a stable common mode voltage as well as an accurate current reference for the driver source / sink current. Maximum operating frequency is 700 MHz.