V-Trans 's LVDS Display interface IP is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source and a display device.
The transmitter converts up to 48bits (single pixel 18bits, single pixel 24bits, dual pixel 18bits, dual pixel 24bits color) of CMOS data into 8 LVDS, (low voltage differential signaling) data streams.
Control signals (VSYNC, HSYNC, DE, and 2 userdefined signals) are sent along with the data stream in DC unbalance mode or during blanking intervals for DC balanced mode.
At a maximum dual pixel rate of 112Mhz, LVDS data line speed is 672Mbps, providing a total throughput of 5.38Gbps (672Megabytes per second).
DC balancing on a cycle-to-cycle basis as described by the openLDI specification is also provided to reduce ISI (Inter-Symbol Interference) in order to obtain a low distortion eye-pattern at the receiver end of the cable.
- 1P6M layout structure based on 0.18um 1P6M 1.8V generic logic process.
- 3.3V/1.8V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 5.38Gbps bandwidth
- DC Balance data transmission for low ISI distortion
- Dual pixel architecture supports interface to GUI and timing controller (dual/single pixel mode)
- Transmitter rejects cycle-to-cycle jitter
- Spread-spectrum input clock support
- Second LVDS clock for backward compatibility w/ FPD link
- Test mode with gray or PRBS patterns generator
- Core cell area : [contact us]
- Built-in power pads with ESD protection.
- Low leakage power-down mode <1uA.
- Reduced swing setting
- Equivalent part : National Semiconductor DS90C387