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Silicon IP Catalog
Analog & Mixed Signal
PLL
General Purpose PLL
> Page 9

General Purpose PLL IP Core

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General Purpose PLL IP Listing

625 IP Cores (361 - 400)

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TSMC CLN80HS 80nm General Purpose PLL - 250MHz-1250MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a ...

361
TSMC CLN80GT 80nm General Purpose PLL - 250MHz-1250MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a ...

362
TSMC CLN80GC 80nm General Purpose PLL - 160MHz-800MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a ...

363
UMC L28HPM 28nm General Purpose PLL - 350MHz-1750MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a ...

364
UMC L28HLP 28nm General Purpose PLL - 220MHz-1100MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a ...

365
PLL IP, Input: 372M - 540MHz, Output: 5MHz - 420MHz, UMC 0.11um HS/FSG process

Input 372M ~ 540MHz, output 5M ~ 420MHz, PLL, UMC 0.11um HS/FSG Logic process.

366
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 25MHz - 400MHz, UMC 0.11um HS/AE process

Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL, UMC 0.11um HS/AE Logic process, It has lock detector function.

367
PLL (Frequency Synthesizer) IP, Input: 10MHz - 50MHz, Output: 10MHz - 200MHz, UMC 40nm LP process

Input 10-50MHz, output 10-200MHz, frequency synthesizable PLL, UMC 40nm LP/RVT Logic process.

368
PLL (Frequency Synthesizer) IP, Input: 10MHz - 50MHz, Output: 10MHz - 200MHz, UMC 40nm LP process

Input 10-50MHz, output 10-200MHz, frequency synthesizable PLL, UMC 40nm LP/RVT Logic process(Note:same schematic with FXPLL010HH0L, but Poly Density Errors are waived in layout for 40% area ...

369
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 55nm LP process

Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 55nm LP/RVT Low-K Logic process.

370
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process

Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process.

371
PLL (Frequency Synthesizer) IP, Input: 10MHz-200MHz, Output: 25MHz - 400MHz, UMC 0.11um MS process

Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um Logic/MIXEDMODE AE process.

372
PLL (Frequency Synthesizer) IP, Input: 10MHz-200MHz, Output: 25MHz - 400MHz, UMC 0.11um MS process

Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um Logic/MIXEDMODE AE process.

373
PLL (Frequency Synthesizer) IP, Input: 10MHz-200MHz, Output: 25MHz - 400MHz, UMC 0.11um SP/FSG process

Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um SP/FSG Logic process.

374
PLL (Frequency Synthesizer) IP, Input: 12MHz, Output: 96MHz - 180MHz, UMC 0.11um HS/AE process

Input 12MHz, output 96M~180MHz, 1.08~1.32V frequency synthesizable PLL, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process.

375
PLL (Frequency Synthesizer) IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, 400MHz - 800MHz, 800MHz - 1600MHz, UMC 40nm LP process

Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz, frequency synthesizable PLL, UMC 40nm LP/RVT Low-K Logic process.

376
PLL (Frequency Synthesizer) IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, 400MHz - 800MHz, 800MHz - 1600MHz, UMC 55nm LP process

Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz, frequency synthesizable PLL, UMC 55nm LP/RVT Low-K Logic process.

377
PLL (Frequency Synthesizer) IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, 400MHz - 800MHz, 800MHz - 1600MHz, UMC 65nm LP process

Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz, frequency synthesizable PLL, UMC 65nm LP/RVT Low-K Logic process.

378
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.11um HS/AE process

Input 20M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process.

379
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 40nm LP process

Input 20M-200MHz, output 500M-1GHz, frequency synthesizable PLL, UMC 40nm LP/RVT Low-K Logic process.

380
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 0.11um HS/FSG process

Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 0.11um HS/FSG Logic process.

381
PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 28nm HPM process

Input 25-66MHz, output 400-800MHz, frequency synthesizable PLL, UMC 28nm HPM Logic process.

382
PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 40nm LP process

Input 25M-66MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 40nm LP/RVT Logic process.

383
PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 55nm LP process

Input 25M-66MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 55nm LP/RVT Low-K Logic process.

384
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 90nm LL process

Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 90nm LL/RVT process.

385
Phase frequency detector and charge pump

The device consists of phase frequency detector (PFD), charge pump and lock detector (LD). PFD compares phases of a divided VCO signal and a divided reference oscillator signal. PFD feeds ...

386
5-bit programmable ECL high-frequency divider

The 5-bit programmable ECL high-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 that is able to scale the structure either into minimum dividing ...

387
Phase frequency detector and charge pump

Phase-frequency detector (PFD) is used to form a control signal VCO tuning. PFD compares phases of divided VCO signals and divided reference oscillator signals and detects phase difference. ...

388
Phase-frequency detector in CMOS logic

The phase-frequency detector (PFD) consists of a signal level converter from differential reduced swing ECL to single-ended full swing CMOS signal and two D-flip-flops with reset, made in CMOS ...

389
9-bit programmable ECL HF divider

The 9-bit programmable ECL high-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 which is able to scale the structure either into minimum dividing ...

390
4-bit programmable ECL LF divider (1…15 dividing ratio )

The 4-bit programmable ECL low-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 which is able to scale the structure into maximum dividing ratio increasing. ...

391
24.84 MHz phase-frequency detector with charge pump

The device consists of phase frequency detector (PFD), charge pump and lock detector (LD) PFD compares phases of a divided VCO signal and a divided reference oscillator signal. PFD feeds control ...

392
2693 to 3753 MHz Voltage controlled oscillator

Voltage-controlled oscillator (VCO) is the generator that can be tuned over a wide range of frequencies by applying a control voltage to it. The block is fabricated on AMS BiCMOS 0.35 um techology ...

393
2096 to 2916 MHz Voltage controlled oscillator

Voltage-controlled oscillator (VCO) is the generator that can be tuned over a wide range of frequencies by applying a control voltage to it. The block is fabricated on AMS BiCMOS 0.35 um techology. ...

394
Minimum-area low-power clocking PLL (1st gen)

Perceptia’s DeepSub™ pPLL02 is a general purpose all digital PLL featuring low-jitter and compact area suitable for many clocking applications at frequencies up to 2GHz. It is suitable as ...

395
4-GHz Jitter-optimized low-power digital PLL

Perceptia’s DeepSubTM pPLL03 series PLLs are low-cost low-power low-jitter PLLs, for foundry processes from 28 to 180-nm. They are typically used together with the companion IPs pREG01 regulator ...

396
Minimum-area low-power clocking PLL (1st Gen)

Perceptia’s DeepSub™ pPLL02 is a general purpose all digital PLL featuring low-jitter and compact area suitable for many clocking applications at frequencies up to 2GHz. It is suitable as ...

397
1.5-GHz Jitter-optimized low-power digital PLL

The DeepSub pPLL03 series PLLs are low-cost low-power low-jitter PLLs, for foundry processes from 28 to 180-nm. They are typically used together with the companion IPs pREG01 regulator and pDIV ...

398
High-Speed, Wide-Range Digital PLL in TSMC 40LP

Granite Semicom has just shipped GDS-II of its totally-integrated (no off-chip components) Clock-Driver and Clock-Multiplying-Unit IP block including fractional-N in TSMC’s 40LP process; silicon ...

399
Wide-Range Low-Area Digital PLL in TSMC 28HPM

Granite SemiCom Inc. (GSC) has just completed the design, layout, and verification, of it’s digitall PLL (DPLL) for realization in TSMC’s 28nm HPM process; this is GSC’s third DPLL (developed ...

400

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