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Silicon IP Catalog
Analog & Mixed Signal
PLL
General Purpose PLL
> Page 9

General Purpose PLL IP Core

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General Purpose PLL IP Listing

600 IP Cores (361 - 400)

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UMC L40LP 40nm Ultra PLL - 15MHz-3250MHz

The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, features and ease of use. It is highly programmable ...

361
UMC L28HLP 28nm Ultra PLL - 15MHz-3250MHz

The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, features and ease of use. It is highly programmable ...

362
TSMC CLN65LP 65nm Ultra PLL - 15MHz-3250MHz

The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, features and ease of use. It is highly programmable ...

363
TSMC CLN40LP+ 40nm Ultra PLL - 15MHz-3250MHz

The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, features and ease of use. It is highly programmable ...

364
TSMC CLN28HP 28nm Ultra PLL - 15MHz-3250MHz

The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, features and ease of use. It is highly programmable ...

365
TSMC CLN16FFCLL 16nm General Purpose PLL - 400MHz-2000MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a ...

366
TSMC CLN16FF+LL 16nm General Purpose PLL - 400MHz-2000MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a ...

367
TSMC CLN16FF+GL 16nm General Purpose PLL - 400MHz-2000MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a ...

368
TSMC CLN16FFCLLLVT 16nm General Purpose PLL - 600MHz-3000MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a ...

369
TSMC CLN16FF+LLLVT 16nm General Purpose PLL - 600MHz-3000MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a ...

370
TSMC CLN16FF+GLLVT 16nm General Purpose PLL - 600MHz-3000MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a ...

371
TSMC CLN28HPC+LVT 28nm General Purpose PLL - 450MHz-2250MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a ...

372
GF L55LPX 55nm General Purpose PLL - 120MHz-600MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a ...

373
TSMC CLN12FFCLLLVT 12nm Ultra PLL - 15MHz-3250MHz

The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, features and ease of use. It is highly programmable ...

374
TSMC CLN22ULP 22nm Ultra PLL - 15MHz-3250MHz

The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, features and ease of use. It is highly programmable ...

375
UMC L28HPC+LVT 28nm Ultra PLL - 15MHz-3250MHz

The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, features and ease of use. It is highly programmable ...

376
SMIC 0.18um 1.8v APLL

This IP is a programmable Analog PLL suitable for low frequency reference clock and large feedback clock divider. It contains a 1-32 input clock divider, a 1024-4578 feedback clock divider and ...

377
GLOBALFOUNDRIES 0.11um 1.2v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO of this PLL can run up to 1000MHz. It contains a 1-64 input clock divider, a 1-128 feedback ...

378
GLOBALFOUNDRIES 0.13um 1.2V POR

Present Power on Reset generates system reset signal (RESET and RESETN) when 1.2V power (POR_VDD) rises to a specific level, i.e., Vtr.

379
GLOBALFOUNDRIES 40nm Low Power 1.1v/2.5v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 300MHz to 900MHz. By setting DM[3:0], DN[6:0] and DP[1:0] to different values according ...

380
Wide Tuning Range Ultra-Low Phase Noise Delta Sigma Fractional-N LC PLL

Wide-Range programmable fractional-N delta sigma LC based frequency synthesizer intended for RF LO synthesis or high performance clock generation applications.

381
IGAPLLT08A, TSMC CLN28HPC & CLN28HPC+ General Purpose PLL

The IGAPLLT08A is a general purpose deskew Phase Locked Loop (PLL) without external component. It is designed to provide a stable and accurate reference clock for digital circuitries. Broadly, ...

382
PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.15um SP process

Input 5M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.15um SP Logic process.

383
PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.15um SP process

Input 5M-200MHz, output 20M-300MHz, frequency synthesizable PLL with power/ground pad, UMC 0.15um SP Logic process.

384
PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 60MHz - 200MHz, UMC 0.18um G2 process

Input 5M-200MHz, output 60M-200MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.

385
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.162um LL process

Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.162um Logic process.

386
PLL (Frequency Synthesizer) IP, Input: 12MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process

Input 12M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.

387
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process

Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL with power/ground pad, UMC 0.18um GII Logic process.

388
Clock and Data Recovery of HDB3/B3ZS coded signals

An all-digital solution suitable for clock/data recovery of HDB3/B3ZS coded signals.

389
Phase-frequency detector in CMOS logic

The phase-frequency detector (PFD) consists of a signal level converter from differential reduced swing ECL to single-ended full swing CMOS signal and two D-flip-flops with reset, made in CMOS ...

390
Ultra low power crystal oscillator 32.768 kHz

055UMC_OSC_01 is a crystal oscillator with Pierce architecture. The block implementation is optimized for very low power consumption. The block consists of a feedback amplifier and buffers ...

391
Minimum-area low-power clocking PLL (1st Gen)

Perceptia’s DeepSub™ pPLL02 is a general purpose all digital PLL featuring low-jitter and compact area suitable for many clocking applications at frequencies up to 2GHz. It is suitable as ...

392
1.5-GHz Jitter-optimized low-power digital PLL

The DeepSub pPLL03 series PLLs are low-cost low-power low-jitter PLLs, for foundry processes from 28 to 180-nm. They are typically used together with the companion IPs pREG01 regulator and pDIV ...

393
4-GHz Jitter-optimized low-power digital PLL

Perceptia’s DeepSub pPLL03 series PLLs are low-cost low-power low-jitter PLLs, for foundry processes from 28 to 180-nm. They are typically used together with the companion IPs pREG01 regulator ...

394
General Purpose Fractional-N PLL in GlobalFoundries 22FDX

Perceptia’s DeepSub™ pPLL02F is a general purpose PLL featuring low-jitter and compact area suitable for many clocking applications at frequencies up to 2GHz. It is suitable as a clock source ...

395
Low Jitter 1.25GHz to 2.5GHz Quadrature Output PLL

The Clock generator PLL is designed to multiply an input clock signal by an integer 40 and 50. It does not provide any de-skew functionality . The output is 2.5GHz with 50% duty cycle with quadrature ...

396
Phase Locked Loop (PLL) Frequency Synthesizer Core

For general purpose Phase Locked Loops (PLL), ASIC designers have to rely on analog VCOs until today. Now Cologne Chip has come up with a fully digital approach: C3-PLL-2, an IP core for frequency ...

397
Audio PLL - Fractional-N ±0.05 ppm accuracy

This PLL can generate all the frequencies used by audio systems from a stable clock of 10 to 40Mhz. Audio clock is 256*fs0 or 384*fs1, where fs0 is 192kHz or 176.4kHz and fs1 is 96kHz or 88.2Khz. ...

398
0.1 to 1 GHZ Frequency Divider

399
High Performance PLL for U3 devices

400

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