The 9-bit programmable ECL high-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 which is able to scale the structure either into minimum dividing ratio decreasing or maximum dividing ratio increasing. The differential circuit has higher noise immunity.
The block is fabricated on AMS BiCMOS 0.35 µm technology.
- AMS BiCMOS 0.35 µm
- Differential structure
- Dividing ratio is regulated in the range of 8...511 with step 1
- Input differential signal frequency up to 1.7 GHz
- Scalable structure
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- PLL frequency synthesizer