Low latency Network TAP IP-Core for full duplex 100M/1G Ethernet links
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Phase-frequency detector in CMOS logic
The phase-frequency detector (PFD) consists of a signal level converter from differential reduced swing ECL to single-ended full swing CMOS signal and two D-flip-flops with reset, made in CMOS logic. Multiplexer allows to switch the input signals to the corresponding inputs.
The block is fabricated on AMS BiCMOS 0.35 um technology.
The block is fabricated on AMS BiCMOS 0.35 um technology.
特色
- AMS BiCMOS 0.35 um
- Ability to work with VCOs with both positive and negative frequency dependence of the control voltage
- Input frequencies up to 100 MHz
- Differential CMOS output signal
- CMOS output signal for lock detector
- Built-in reset delay circuit
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
可交付内容
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
应用
- Phase-locked loop synthesizer
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