USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
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PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 0.11um HS/FSG process
Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 0.11um HS/FSG Logic process.
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