4-GHz Jitter-optimized low-power digital PLL

特色

• - Jitter below 10-ps
• - Super small: 90 x 90 microns!
• - Very low power: 15-mW
• - Broad frequency range: 4-GHz
• - Fast lock
• - Lock detect
• - Preprogrammed loop filter
• - BIST
• - Scan testable
• - Power-down mode
• - Decoupling caps for lower jitter
• - Available with companion LDO regulator IP

可交付内容

• The pPLL03 series PLL macros are delivered with:
• - Detailed datasheet including guidance for layout, packaging and production test
• - Characterization report or post-layout corner simulation report
• - LEF abstract for floor planning/chip assembly
• - GDSII layout macrocell
• - Spice/CDL netlist (encrypted format) for LVS
• - DRC / SI verification report
• - Verilog model
• - Timing model (.lib)
• - Test vectors and test guidelines
• - Integration support

Block Diagram of the 4-GHz Jitter-optimized low-power digital PLL

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