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SDIO-HOST Controller IP Listing

2756 IP Cores (321 - 360)

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Power Controller RTL IP

MAESTRO is a unique Power Controller RTL IP that features breakthrough capabilities compared to traditional HW or SW PMU design methodologies. It combines the configurability of a software PMU ...

321
DDR3 SDRAM Memory Controller

The logiMEM DDR3 SDRAM Memory Controller is a size optimized, flexible, parametric and synthesizable Synchronous DRAM Controller that supports industry standard Double Data Rate 3 (DDR3) SDRAM ...

322
Gigabit Ethernet 802.3 MAC - Media Access Controller

The Gigabit Ethernet Media Access Controller with AHB Interface IP core is compliant to the Ethernet/IEEE 802.3-2008 standard. The Gigabit Ethernet - AHB IP Core provides a 10/100 Mbps Media ...

323
I3C Master / Slave Controller - MIPI Basic v1.0

The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – BASIC v1.0 Improved Inter Integrated Circuit ...

324
NFC/RFID Controller

NT1046 is a single-chip RFID reader solution. It is composed of an integrated RF front-end, RFID framing engine supporting ISO15693, ISO14443A*, ISO14443B and NFCIP standards, 128-byte FIFO, ...

325
Enhanced Services Controller - Performance Monitoring

The MESC_PM3X function, implemented on a Spartan II FPGA, is to extend the functionnality already available within the APC. This macro can be customized according to specific needs (application-specific ...

326
Enhanced Services Controller - Statistics Controller

The MESC_ST-5A function, implemented on a Cyclone II FPGA, is to extend the functionnality already available within the APC. This macro can be customized according to specific needs (application-specific ...

327
Enhanced Services Controller - Statistics & Performance

Adjunct device to the Agere Systems ATM Port Controller (APC version 3b) in Virtex II FPGA ; Extends the statistics available to the microprocessor ; Directly connected to the Transmit ESI ...

328
Enhanced Services Controller - Statistics Monitor

The MESC_ST3X function, implemented on a Virtex II FPGA, is to extend the functionnality already available within the APC. This macro can be customized according to specific needs (application-specific ...

329
SPI Master - EEPROM Controller

The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI slave. The MSPIM IP can be programmed to run either in standard ...

330
16Bit 91dB Audio CODEC with headphone drivers and PWM Controller, SMIC0.18um

AR34S3E is a mass-production proven sigma-delta mono CODEC designed for portable device applications. It contains PWM (pulse-width-modulated) controller that allows users to configure class-D ...

331
Serial ATA Dual Host Controller

The LDS_SATA HOST DUAL XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XV5 IP is compliant with Serial ATA II specification ...

332
SATA Host controller on Virtex 5 FXT

The LDS SATA HOST XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is compliant with Serial ATA II specification ...

333
Dual SATA Host controller on Virtex 5 FXT FPGA

The LDS SATA HOST DUAL XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XF5 IP is compliant with Serial ATA II specification ...

334
SATA Host Controller

The LDS SATA HOST STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Startix IV GX FPGA. The LDS SATA HOST STR4GX IP is compliant with ...

335
SATA Host Controller on Spartan 6 LXT FPGA

The LDS SATA HOST SP6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Spartan 6 FPGA. The LDS SATA HOST SP6 IP is compliant with Serial ATA II specification ...

336
SATA Host Controller on Virtex 6 LXT

The LDS SATA HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA HOST XV6 IP is compliant with Serial ATA II specification ...

337
SATA III HOST Controller on Virtex 6

The SATA III HOST Controller IP Core incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 speed grade 2 FPGA. The SATA III HOST Controller IP Core is compliant ...

338
SATA Device Controller on Altera Arria II GX

The SATA Device Controller IP Core incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The SATA Device Controller IP Core is ...

339
SATA HOST Controller on Cyclone IV GX

The LDS SATA HOST C4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Cyclone IV GX FPGA. The LDS SATA HOST C4GX IP is compliant with ...

340
SATA Host 6G Controller on Kintex 7

The SATA Host 6G Controller IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 speed grade 2 FPGA. The SATA Host 6G Controller IP is compliant with Serial ...

341
SATA 3 Host Controller on ZYNQ

The LDS SATA 3 HOST XZ7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA. The LDS SATA 3 HOST XZ7 IP is compliant with Serial ATA III ...

342
SATA Device Controller on Kintex 7

The SATA Device IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 FPGA. The SATA Device IP is compliant with Serial ATA III specification ...

343
ZYNQ SATA 3 AHCI Host Controller with Linux Driver

The LDS SATA 3 HOST AHCI XZ7 IP incorporates the AHCI registers model, the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA. The LDS_SATA 3 HOST AHCI XZ7 ...

344
SATA 3 Host Controller on ARRIA V FPGA

The SATA 3 Host Controller IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Stratix IV GX FPGA. The SATA 3 Host Controller IP is compliant ...

345
Virtex 7 GTX SATA 3 Host Controller

The LDS SATA 3 HOST XV7X IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 7 GTX speed grade 2 FPGA. The LDS SATA 3 HOST XV7X IP is compliant with Serial ...

346
SATA 3 Host Controller on Xilinx Artix 7

The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS_SATA3_HOST_XA7 IP is compliant with Serial ATA III ...

347
Super Speed USB 3.0 Extensible Host Controller xHCI

Complies with USB 3.0 Standard for Super Speed (5 Gbps), High Speed (480 Mbps), Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps). ; Complies with Intel xHCI specification for USB (revision 0.9). ; ...

348
I2C Master Serial Interface Controller

Master serial interface compatible with the popular Philips® I2C standard. Features a simple command interface and permits multiple I2C slaves to be controlled directly from your FPGA, CPLD ...

349
I2C Slave Serial Interface Controller

Slave serial interface compatible with the popular Philips® I2C standard. Permits an I2C Master to communicate with your FPGA, CPLD or ASIC device. Auto-detects standard (100 kbits/s), fast ...

350
Parallel FLASH Memory Controller

JEDEC® compliant FLASH memory controller ideal for interfacing to a wide range of parallel FLASH memory components such as the popular SST39 series from Microchip®. Features a fully synchronous ...

351
UART to I2C Bridge Controller

Allows simple connectivity between a UART 2-wire port (Tx/Rx) and an I2C compatible bus. Allows simple programming and debug of an I2C device using a remote PC.

352
USB 2.0 Device Controller

The USB 2.0 Device Controller IP Core is an USB 2.0 compliant device core with optional PCI, Custom, or AHB master/slave interfaces. The USB 2.0 device core supports 480 Mbit/s in High Speed ...

353
USB 2.0 Hub Controller

The Arasan USB 2.0 Hub IP core is an USB 2.0 specification compliant hub core that supports 480 Mbit/s in High Speed (HS) mode, 12 Mbit/s in Full Speed (FS) mode, and 1.5 Mbit/s in Low Speed ...

354
USB 2.0 EHCI Host Controller IP

The Arasan USB 2.0 Host IP is an USB 2.0 specification compliant host IP core with an optional AHB, PCI, or custom host interface. The USB 2.0 Host IP supports 480 Mbit/s in High Speed (HS) ...

355
MIPI SLIMbus Host Controller v2.0

The MIPI SLIMbus Host typically resides in a mobile platform’s application processor and provides two-wire, multi-drop connectivity with multiple audio and other low/mid bandwidth peripheral ...

356
MIPI SLIMbus Device Controller V2.0

The MIPI SLIMbus Device Controller IP is designed to provide MIPI SLIMbus 1.01 compliant connectivity for a peripheral device, like an audio codec, to a SLIMbus compliant host, like an Applications ...

357
MIPI UniPro Controller - v1.6

The MIPI UniPro Controller IP core is fully compliant to UniPro Specification, it implements the UniPro Physical Adapter, Data Link, Network,and Transport layers. A variety of high-performance ...

358
SD/SDIO/MMC Host Controller

A complete, easy to integrate and cost-effective IP core featuring SD/SDIO/MMC Host Controller Interface, for SoC/PDA applications that connect to SD/MMC memory cards and SDIO/combo devices ...

359
Serial Controller Interface

The SCI Slave is a synthesizable, flexible, and structured VHDL implementation of a Serial Controller Interface (SCI) that uses a two-wire bus for communicating between integrated circuits or ...

360

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