Scalable, On-Die Voltage Regulation for High Current Applications
DDR3 SDRAM Memory Controller
“Easy-to-use” parameters and the synthesis for different requirements, optimized for area and speed, auto-routed design makes this IP Core especially suitable for AMD-Xilinx 7 Series FPGA/SoC designs featuring AXI4 bus architecture. It enables an easy connection of processor cores, as well as various peripheral cores, to DDR3 memory chips via AXI4 slave system interface port.
The logiMEM IP Core is fully embedded into the AMD-Xilinx Vivado toolset, and its parametrizable VHDL design allows tuning of slice consumption and features set through an easy-to-use GUI interface. The logiMEM can be smoothly integrated with other logicBRICKSTM IP cores for building of advanced GUI embedded systems.
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