The MESC_ST-5A function, implemented on a Cyclone II FPGA, is to extend the functionnality already available within the APC.
This macro can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.
- Adjunct device to the Lucent ATM Port Controller (APC version 3b and above) in Cyclone II FPGA
- Extends the statistics available to the microprocessor
- Directly connected to the Transmit ESI Interface of one APC
- Maintain Per Connection Statistics for up to 65535 connections simultaneously
- Ingress Received Cells CLP P (e_stat_0) - 32-bits
- Ingress Cells Discarded due to Buffer management CLP P (e_stat_1) - 32-bits
- Ingress Cells Discarded due to Policing CLP P (e_stat_2) - 32-bits
- Ingress Cells Tagged due to Policing (e_stat_3) - 32-bits
- Ingress Cells Discarded with ATM header Errors (e_stat_4) - 32-bits
- Egress Transmitted Cells CLP P (e_stat_5) - 32-bits
- Egress Cells Discarded due to Buffer management CLP P (e_stat_6) - 32-bits
- Simple address and data CPU interface with Ready signal
- Available in VHDL source code format for ease of customization
- Can be customised by Logic Design Solutions
- VHDL Source code or Bitsream
- VHDL Test Bench for behavioural and gate level simulation.
- Data SheetUser’s guide : Simulation, Synthesis and Place and Route procedures.
- Constraint File