The MESC_PM3X function, implemented on a Spartan II FPGA, is to extend the functionnality already available within the APC.
This macro can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.
- Adjunct device to the Agere Systems ATM Port Controller (APC version 3b) in Spartan II FPGA
- PM function can be carried out anywhere in the connection
- Extends the functionnality already available within the APC
- Directly connected to the Transmit ESI Interface of a single APC
- Maintain a different set of per VC statistics for up to 127 connections simultaneously
- Ingress Received Cell Blocks (for convenience called - Stat 0) – 32-Bits
- Ingress Severely Errored Cell Blocks (Bellcore GR1248 PM - Stat A) – 16-Bits
- Ingress CLP0+1 Errored Cells (Bellcore GR1248 PM - Stat B) – 16-Bits
- Ingress Lost CLP0+1 User Information Cells (Bellcore GR1248 PM - Stat C) – 16-Bits
- Ingress Misinserted CLP0+1 User Information Cells (Bellcore GR1248 PM - Stat E) – 16-Bits
- Ingress Total Transmitted CLP0+1 User Information Cells (Bellcore GR1248 PM - Stat F) - 32 bits
- Handle four Block size type per connection : 128, 256, 512 and 1024 cells
- Handle independant threshold for Lost, Misinserted and Errored statistics
- Address and data 48 Mhz CPU interface with Ready signal
- Available in VHDL source code format for ease of customization
- Can be customised by Logic Design Solutions
- VHDL Source code or Bitstream
- VHDL Test Bench for behavioural and gate level simulation.
- Data SheetUser’s guide : Simulation, Synthesis and Place and Route procedures.
- Constraint Files