The USB 3.1 SSIC controller is a highly configurable core and implements the USB 3.1 SSIC functionality that can be interfaced with third party M-PHY's. The SSIC Controller core is architected to seamlessly integrate with either in-house developed SS Host/Device Controller cores or with standard 3rd party SS Host/Device Controller cores. The SSIC Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications. The controller when integrated with in-house Device/xHCI Host controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications. The controller is simple, configurable and modular architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. This solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally.