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USB 3.0 OTG High / Full / Low- Speed Dual Role IP Core
USB 3.0 OTG Controller IP is based on the latest USB 3.0 specification from USB Implementer Forum (USBIF) and is compatible with the latest xHCI 1.1 specification. It supports SuperSpeed (5Gbps) link speed, backward compatible with HighSpeed (480Mbps), FullSpeed (12Mbps) and LowSpeed
(1.5Mbps). USB 3.0 Controller IPs are based on a nextgeneration unified architecture which is designed directly for USB 3.0 specification and optimized intensively for logic sharing.
(1.5Mbps). USB 3.0 Controller IPs are based on a nextgeneration unified architecture which is designed directly for USB 3.0 specification and optimized intensively for logic sharing.
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Block Diagram of the USB 3.0 OTG High / Full / Low- Speed Dual Role IP Core
USB IP IP
- USB 3.0 femtoPHY in TSMC (28nm, 16nm, 12nm)
- USB 3.0 femtoPHY, Type-C in TSMC (28nm, 16nm, 12nm)
- USB 3.0 PHY in TSMC (65nm, 55nm, 40nm, 28nm)
- USB 3.1 PHY (10G/5G) in TSMC (16nm, 12nm, 7nm, 5nm)
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- Fully Self-contained Single/Multi Port USB Type-C Power Delivery IP