Scalable, On-Die Voltage Regulation for High Current Applications
USB 2.0 PHY IP,在 UMC 40LP 中经过硅验证
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Block Diagram of the USB 2.0 PHY IP,在 UMC 40LP 中经过硅验证
USB 2 in UMC40 IP
- USB 2.0 PHY IP, Silicon Proven in UMC 28HPC
- USB 3.0 PHY IP, Silicon Proven in UMC 40SP
- USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)
- USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC
- USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in SMIC 14SF+
- USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in TSMC 28HPC+