The Physical Coding Sublayer (PCS) IP Core enables transmission and reception of data via 8-Lanes SerDes interface. It is able to multiplex a synchronous digital stream of data over 8 Lanes, while guaranteeing data alignment and super-frame synchronization. The PCS is responsible for idle sequence generation, lane striping and encoding for transmission and decoding, lane alignment and restriping on reception. The PCS uses an 8B/10B encoding for transmission over the link.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.