You are here:
Physical Coding Sublayer (PCS) IP Core
The Physical Coding Sublayer (PCS) IP Core enables transmission and reception of data via 8-Lanes SerDes interface. It is able to multiplex a synchronous digital stream of data over 8 Lanes, while guaranteeing data alignment and super-frame synchronization. The PCS is responsible for idle sequence generation, lane striping and encoding for transmission and decoding, lane alignment and restriping on reception. The PCS uses an 8B/10B encoding for transmission over the link.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
特色
- Highly configurable, more than 30 registers available
- Supports 8 Lanes in TX and 8 Lanes in RX path
- Lane misalignment of up to 8 octets is supported
- 8B10B encoding/decoding applied
- PRBS generation/verification support (both per Lane and per SF payload)
- Per Lane Loopback supported
- Various reference clock support for Ser/Des Lane’s PLL
- Fully synchronous design
Block Diagram of the Physical Coding Sublayer (PCS) IP Core
查看 Physical Coding Sublayer (PCS) IP Core 详细介绍：
- 查看 Physical Coding Sublayer (PCS) IP Core 完整数据手册
- 联系 Physical Coding Sublayer (PCS) IP Core 供应商
PCS IP
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- HaLow 802.11ah Transceiver for IoT
- 10-Gbps Ultra-Low Latency Ethernet MAC & PCS (10GBASE-R)
- 40-Gbps Ultra-Low Latency Ethernet MAC & PCS (40GBASE-R4)
- 100-Gbps Ultra-Low Latency Ethernet MAC & PCS (100GBASE-R4, 100GBASE-R10)
- 25-Gbps Ultra-Low Latency Ethernet MAC & PCS + RS-FEC