100G Ethernet PCS IP
The quad port 100G Ethernet PCS IP can be configured as a 2x100G PCS or a 4x50G/25G/10G PCS interfacing with a 4-lane 56G PHY. The single port IP can be configured as one of 4x25G, 2x50G or 1x100G interfacing with a PHY. The Synopsys 100G Ethernet PCS IP offers a comprehensive set of features including 100G scrambler/descrambler, 64b/66b encoder/decoder, multi-lane distribution, alignment marker insertion/striping, block synchronization and gearbox, and clock decoupling FIFOs. The multiplexed Reed-Solomon Forward Error Correction (RS-FEC) function provides different channels at various speeds. The IP implements a CGMII on the application side and four lanes interface to the PHY on the line side.
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100G Ethernet IP
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