You are here:
40G/100G Ethernet Core
Xilinx 40G/100G Ethernet LogiCORE based on Sarance Technologies Best-In-Class Intellectual Property
Xilinx High-Speed Ethernet LogiCORE® (HSEC) is a high-performance and flexible implementation of the IEEE 802.32012 for 40Gbps and 100Gbps Ethernet. The HSEC implements the 40G and 100G aggregate Physical Coding Sublayer (PCS), and a 40G and 100G Media Access Controller (MAC) module. The HSEC is the world’s first implementation of the IEEE 802.32012 specifications and has been successfully deployed in a major ISP’s network in the USA. Xilinx also sells the CAUI and XLAUI PCS layers standalone with optional Auto_Negotiation and FEC for backplane applications. Xilinx 40G and 100G Ethernet LogiCORE is based on Sarance Technologies Intellectual Property and is delivered as a netlist implemented in UltraScale and Virtex® FPGA families.
Xilinx High-Speed Ethernet LogiCORE® (HSEC) is a high-performance and flexible implementation of the IEEE 802.32012 for 40Gbps and 100Gbps Ethernet. The HSEC implements the 40G and 100G aggregate Physical Coding Sublayer (PCS), and a 40G and 100G Media Access Controller (MAC) module. The HSEC is the world’s first implementation of the IEEE 802.32012 specifications and has been successfully deployed in a major ISP’s network in the USA. Xilinx also sells the CAUI and XLAUI PCS layers standalone with optional Auto_Negotiation and FEC for backplane applications. Xilinx 40G and 100G Ethernet LogiCORE is based on Sarance Technologies Intellectual Property and is delivered as a netlist implemented in UltraScale and Virtex® FPGA families.
特色
- Full 100G and 40G Ethernet line rate operation
- Optional fee based Auto-Negotiation and FEC features for MAC + PCS or standalone PCS IP
- Optional Frame Check Sequence (FCS) checking, adding and deleting
- Static and dynamic de-skew functions
- PCS Lane Marker insertion and deletion
- PCS Lane framing and de-framing including swapping of each PCS Lane
- Inter-Packet Gap (IPG) insertion and deletion as required by 802.32012
- For UltraScale and UltraScale+ 40G Ethernet support, please refer to 40G/50G Ethernet Subsystem
- 40G Ethernet and 50G Ethernet are bundled together
- For 7-Series 40G Ethernet support, please contact ethernet_mgmt@xilinx.com
- For access to the 100G Intergrated Ethernet IP, please refer to the UltraScale Integarated 100G Ethernet Subsystem and UltraScale+ Integrated 100G Ethernet Subsystem product pages
查看 40G/100G Ethernet Core 详细介绍：
- 查看 40G/100G Ethernet Core 完整数据手册
- 联系 40G/100G Ethernet Core 供应商
Interface and Interconnect IP
- FlexNoC Network on Chip SoC Interconnect IP
- Cache Coherent Interconnect
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- Serial Peripheral Interconnect Master & Slave Interface Controller
- Physical Layer Interface Core