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Ethernet PCS 10G/25G
Comcores 10G/25G PCS IP core is a silicon agnostic implementation of the PCS layer described in the Ethernet standard IEEE 802.3-2015 and compliant with Clause 49 of IEEE 802.3ae specification. The IP-core is part of a family of IP-cores that are tightly integrated.
The IP-core has been optimized for size and offers an XGMII interface on one side and a 64-bit interface on the PMA-side.
The IP-core has been optimized for size and offers an XGMII interface on one side and a 64-bit interface on the PMA-side.
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Block Diagram of the Ethernet PCS 10G/25G
Ethernet IP
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- Ethernet Switch / Router IP Core - Efficient and Massively Customizable
- Gigabit Ethernet 802.3 MAC - Media Access Controller
- TCP/IP - 10 &25Gbit Ethernet TCP server/client
- 10 Gb/s full HW stack UDP/IP Transmitter/Receiver
- Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC)