Process Detector (For DVFS and monitoring process variation)
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Ethernet PCS 10G/25G
Comcores Ethernet PCS IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 and with Clause 49 of IEEE 802.3ae specification. The Ethernet PCS IP supports 10G and 25G line rates, however other Ethernet PCS speeds are available, such as 1G/2.5G and 100G.
The PCS IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a XGMII or XXVGMII Interface, and a default 40-bit parallel interface at the PMA-side.
The PCS IP core is verified using advanced methodologies for RTL design, verification, HW verification and interoperability testing. It has been optimized for size and is a highly tested solution that will fast track any project.
The PCS IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a XGMII or XXVGMII Interface, and a default 40-bit parallel interface at the PMA-side.
The PCS IP core is verified using advanced methodologies for RTL design, verification, HW verification and interoperability testing. It has been optimized for size and is a highly tested solution that will fast track any project.
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Block Diagram of the Ethernet PCS 10G/25G
Ethernet IP
- 10G-100G MACsec Security Module for Ethernet
- 224G Ethernet PHY in TSMC (N3E, N2P)
- 112G Ethernet PHY in TSMC (N7, N6, N5, N3P)
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency