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Wireline Communication
Error Correction/Detection
Forward Error Correction
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Forward Error Correction IP Core

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Forward Error Correction IP Listing

82 IP Cores (41 - 80)

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SiFive: MCMR FEC (Forward Error Correction) IP Core

SiFive’s MCMR FEC IP core is a single solution to meet the requirements of different protocols like Interlaken, Flex Ethernet, and 802.3x to significantly improve bandwidth by enabling high ...

41
Parallel Reed-Solomon ECC/FEC RX Custom IP Core

Hardent's ECC/FEC (Error-Correcting Code/Forward Error Correction) proprietary tool suite implements Reed-Solomon algorithms with a high-performance parallel architecture. Hardent uses the ...

42
Parallel Reed-Solomon ECC/FEC TX Custom IP Core

Hardent's ECC/FEC (Error-Correcting Code/Forward Error Correction) proprietary tool suite implements Reed-Solomon algorithms with a high-performance parallel architecture. Hardent uses the ...

43
HDMI 2.1 Forward Error Correction (FEC) Receiver

The HDMI Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol de-interleaving/de-mapping as specified by the HDMI 2.1 specification. Forward Error Correction ...

44
HDMI 2.1 Forward Error Correction (FEC) Transmitter

The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specified by the HDMI 2.1 specification. Forward Error Correction ...

45
VESA DisplayPort 1.4 TX IP Subsystem for Xilinx FPGAs

Complete DisplayPort™ 1.4 Transmitter solution with support for VESA Display Stream Compression (DSC) ; Fully compliant with the DisplayPort 1.4a Standard ; Including the DSC slices per ...

46
VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs

Complete DisplayPort™ 1.4 Receiver solution with support for VESA Display Stream Compression (DSC) ; Fully compliant with the DisplayPort 1.4a Standard ; Including the DSC slices per line ...

47
1Gbit/s LDPC Decoder and Encoder (WiMedia UWB)

The WiMedia 1.5 LDPC Decoder IP supports all LDPC coding schemes as defined by the standard. The WiMedia UWB standard was developed by the WiMedia Alliance. Version 1.5 of the standard introduces ...

48
GMR Release 2 and GMR Release 3 LDPC Decoder

GEO-Mobile Radio (GMR) is an ETSI standard for satellite phones. The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GMR Release 2 (GMPRS-1) and use LDPC codes ...

49
IEEE 802.15.3c (60 GHz PHY) Multi-Gbit/s LDPC Decoder

The Creonic IEEE 802.15.3c LDPC Decoder IP Core supports all LDPC codes with a codeword size of 672 bits as defined by the standard. The IEEE 802.15 working group specifies standards targeting ...

50
2.3 Gbit/s DOCSIS 3.1 Downstream LDPC Decoder (PLC, NCP, Data)

Data Over Cable Service Interface Specification (DOCSIS) is an international telecommunications standard that permits the addition of high-bandwidth data transfer to an existing cable TV (CATV) ...

51
DVB-S2X Wideband Demodulator

The Creonic DVB-S2X high performance wideband demodulator performs all tasks of an inner receiver and achieves throughputs of up to 500 Msymb/s on state-of-the-art FPGAs. The ...

52
Wideband DDC

The Creonic Wideband Digital Down Converter (DDC) digitally converts the input signal at IF frequency down to baseband by multiplying input samples with sine/cosine waves generated by numerical ...

53
CCSDS SCCC Turbo Encoder and Decoder

The recommended CCSDS 131.2-B-1 standard introduces a Serial Concatenated Convolutional Code (SCCC). Main goal of this code is to allow an efficient use of available bandwidth, by allowing to ...

54
Fixed-Point AWGN Channel

The Creonic AWGN Channel IP is a noise generator capable of processing up to a maximum of 512 symbols in parallel. The IP was developed with the aim of allowing the performance evaluation of ...

55
2.5Gbps GPON FEC CORE

Encoder ; Fully compliant with the GPON standard (G.984.3), supports 8-bit, 16-bit or 32-bit input for different data rates, supports short last code word ; Available for FPGA or ASIC ...

56
DVB-S2 Compliant LDPC/BCH Forward Error Correction Core

Low density parity check codes (LDPCs) offer near Shannon Limit performance over a wide range of code rates. AHA now offers LDPC cores ranging from 2 Mbits/sec to over 1 Gbits/s. With these ...

57
CTC encoder - Convolutional Turbo Code encoder for 3GPP (WCDMA)

Rate 1/3, other rates can be achieved with external puncturing. ; Parallel encoder with 2 identical RSCs, constituent code is systematic. ; Compliant with 3GPP (WCDMA 99). ; Support LTE interleave ...

58
CTC decoder - Convolutional Turbo Code decoder for 3GPP (WCDMA)

K=4 (8 states). ; Rate 1/3, other rates can be achieved with external puncturing. ; Sophisticated early termination mechanism to support power saving and higher statistical throughput. ; Compliant ...

59
Rate-1/3 fast Viterbi decoder

Constraint length = 7, rate = 1/3 (default: G0=oct"133", G1=oct"165", G2=oct"171") ; Capable of punctured coding ; 3-bit soft inputs ; Burst and continuous modes ; High speed design, above 200 ...

60
IEEE 802.3an/bz LDPC Encoder-Decoder

The recently published IEEE 802.3an/bz standard describes the 10GBASE-T application for operation over category 6/class E (~50 meter), augmented category 6/class E, and class F twisted-pair ...

61
Configurable Reed Solomon Encoder/Decoder for GF(256) Product Family - supporting Erasue / Error decoding , streaming / burst up to 40gbps

Amethyst provides a novel architecture of RS CODEC targeted for various communication standards. The cores under RSFAMILY support different architecture offering optimization for different ...

62
CMMB LDPC decoder

China Multimedia Mobile Broadcasting (CMMB) LDPC decoder, implemented with Continuous bits’ innovative LDPC-decoder architecture. The implementation provides high data-rates, low power consumption, ...

63
IEEE 802.15.3c Irregular LDPC(672,336), LDPC(672,504), LDPC(672,588) encoder and decoder

IEEE802.15.3c irregular LDPC(672,336), LDPC(672,504), LDPC(672,588) encoder and decoder. The implementation provides: (a) High throughput. Datarates higher than the raw data rates of single ...

64
3GPP LTE TCC decoder

Rate 1/3, other rates can be achieved with external puncturing. ; Implements the 3GPP Long Term Evolution (LTE) specification. ; Core contains the full 3GPP LTE interleaver. ; All 188 3GPP LTE ...

65
3GPP LTE TCC encoder

Rate 1/3, other rates can be achieved with external puncturing. ; Implements the 3GPP LTE specification. ; Core contains the full 3GPP LTE interleaver. ; All 188 3GPP LTE block sizes (40 - 6144) ...

66
802.11n (MIMO WLAN) LDPC decoder / encoder

Code length: 648, 1296, 1944. ; Code rates: 1/2, 2/3, 3/4, 5/6 (for each code length). ; Programmable number of iterations. ; Internal convergence test stops the decoder when data is fully recovered ...

67
DVB-S2 LDPC decoder

Supports CCM, VCM, ACM modes. ; Supports 64Kbit and 16Kbit frames. ; 0.1dB to 0.5dB coding gain improvement versus the standard reference. ; Frame by frame programmability of code rate, modulation, ...

68
China Multimedia Mobile Broadcasting (CMMB) LDPC decoder

Compliant with CMMB specifications, block size of 9216 bits, code rates 1/2 and 3/4. ; Frame by frame programmability of code rate and number of iterations. ; Syndrome based LDPC iteration stopping ...

69
tail-biting Viterbi decoder (rate 1/5) for 802.16m

K=7 (64 states) G1=171(octal), G2=133(octal), G3=165(octal), G4=117(octal), G5=127(octal). ; Rate 1/5. Other rates can be supplied by external puncturing. ; Support WiMAX rate 1/2 and LTE rate ...

70
Dual mode WiMAX/LTE turbo decoder

Implements the WiMAX IEEE802.16e/m and 3GPP Long Term Evolution (LTE) specifications.

71
IEEE802.3bj RS-FEC Decoder for 100Gb/s Application

The RS-FEC Decoder IP is a highly optimized Reed Solomon Decoder solution designed for the IEEE 802.3bj standard. The Reed Solomon codeword can be fed partially parallelized to the Decoder ...

72
Complete FEC Encoder Solution compliant to LTE/ LTE A Specification

The 3GPP LTE FEC Encoder IP Core addresses the implementation of the FEC building blocks compliant to 3GPP TS 36.212 V 10.5.0. Specifically, the IP core offers an efficient, easy to customize ...

73
WCDMA Release 9 compliant Viterbi Decoder

The 3GPP WCDMA Viterbi Decoder IP Core V1.0 addresses the implementation of the Viterbi Decoder defined as part of the Forward Error Correction block compliant to 3GPP TS 25.212 V 9.5.0

74
DVB-S2X Compliant LDPC/BCH Decoder IP Core

The AHA4709D LDPC/BCH forward error correction (FEC) decoder core supports all codes, frame sizes, and interleave schemes set forth in the DVB-S2X specifications for broadcast, interactive, ...

75
DVB-S2X Compliant LDPC/BCH Encoder IP Core

The AHA4709E LDPC/BCH forward error correction (FEC) encoder core supports all codes, frame sizes, and interleave schemes set forth in the DVB-S2X specifications for broadcast, interactive, ...

76
DVB-S2X Compliant LLR Demapper IP Core

The AHA4709L LLR Demapper core is compliant with section 5.4* (see Note 1) of the Digital Video Broadcast S2-Extention (DVB-S2X) standard. By default, this core uses re-labeled constellation ...

77
10G I.9 BCH Encoder/Decoder for ITU G.975.1

The IPrium-10G-I.9-BCH-Codec IP core implements "two interleaved extended BCH" super-FEC code for optical lines and is fully compatible with ITU-T G.975.1 (super-FEC for 2.5G, 10G and 40G optical ...

78
Least-Area 10GBase-KR Ethernet FEC/AN Core

The 10GBase-KR Core attaches directly to our 10GBase-R Medium Access Controller and Physical Coding Sublayer Core. It provides 10Gb/s FEC-protected transmission using Xilinx Series 7 FPGAs. ...

79
ASIC IP-core for very-high-throughput decoding (>20G) of 3GPP 5G Release 15

Very high throughput (>20 Gbps) LDPC decoder and encoder for 3GPP 5G Release 15. It supports both base-graphs, and all rates.

80

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