The Creonic DVB-S2X wideband decoder is a scalable solution that allows for symbol rates of up to 500 MSymb/s on state-of-the-art FPGAs
- Compliant with DVB-S2 and DVB-S2X
- Support for decoding of BBFRAMEs
- Support for ACM, CCM, and VCM
- Support for short and normal frames (16 200 bits and 64 800 bits)
- Support for QPSK, 8-PSK, 16-APSK, 32-APSK, 64-APSK, 128-APSK, and 256-APSK
- Validated against 3rd party DVB-S2X modulators.
- Based on industry-proven design for DVB-S2.
- Soft-Decision demapper, block deinterleaver, LDPC decoder, BCH decoder, and descrambler included.
- Low-power and low-complexity design.
- Frame-to-frame on-the-fly configuration.
- Design-time configuration of throughput for optimal resource utilization.
- Faster convergence due to layered LDPC decoder architecture.
- Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy.
- Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance with on-the-fly selection in ACM/VCM modes.
- Collection of statistics (error rates, average number of iterations, signal-to-noise ratio (SNR)).
- Available for ASIC and FPGAs (Xilinx, Intel).
- VHDL source code or netlist
- HDL simulation models
- VHDL testbench
- bit-accurate Matlab, C or C++ simulation model
- comprehensive documentation
- Satellite Communications
- Applications with highest demands on forward error correction
- Applications with the need for a wide range of code rates (1/5 to 9/10)
Block Diagram of the DVB-S2X Wideband LDPC/ BCH Decoder