The Creonic DVB-S2X high performance wideband demodulator performs all tasks of an inner receiver and achieves throughputs of up to 500 Msymb/s on state-of-the-art FPGAs. The demodulator expects the quantized, complex baseband samples from an analog-digital-converter (ADC) and recovers timing, frequency and phase of the complex mapped symbols. In addition the core handles PL frame recovery and PL de-framing. The output of the demodulator perfectly fits the Creonic DVB-S2X forward error correction IP core that implements LDPC and BCH decoding.
- Compliant with DVB-S2 and DVB-S2X
- Supports ACM, CCM, and VCM modes
- Support for short and long blocks (16,200 bits and 64,800 bits)
- Support for QPSK to 256-APSK,
- VLSNR modes on request.
- Output of XFECFRAMEs for further processing by the Creonic FEC decoder.
- Validated against 3rd party DVB-S2X modulators.
- Contains radio interface, decimator, timing recovery, equalizer, frame acquisition, and carrier recovery.
- Performs and supports spectrum inversion, DC offset correction, I/Q imbalance correction, decimation, coarse frequency estimation, timing recovery, matched filtering, downsampling, frame synchronization, PL descrambling, fine frequency correction, phase correction, automatic gain control, and PL deframing.
- Low-power and low-complexity design.
- On-the-fly configuration.
- Memory mapped interface for controlling the core and for retrieving status information.
- Very fast synchronization due to different sets of filter coefficients for acquisition and tracking mode.
- Configurable interrupts and output of synchronization status information.
- Perfectly fits to the Creonic DVB-S2X LDPC/BCH decoder.
- Available for ASIC and FPGAs (Xilinx, Intel)
- VHDL source code or synthesized netlist
- HDL simulation models
- Bit-accurate Matlab, C or C++ simulation model
- Comprehensive documentation
- Satellite communication
- Digial Video Broadcasting
- Interactive Services
- Professional Services
- News Gathering
Block Diagram of the DVB-S2X Wideband Demodulator