You are here:

10G I.3 BCH Encoder/Decoder for ITU G.975.1

The IPrium-10G-I.3-BCH-Codec IP core implements "Concatenated BCH super FEC" with BCH(3860, 3824) and BCH(2040, 1930) forward error correction algorithms for optical lines and is fully compatible with ITU-T G.975.1 (super-FEC for 2.5G, 10G and 40G optical networks).

特色

Fully synchronous design, using single clock
Fully synthesizable drop-in module for FPGAs
Optimized for high performance and low resources
Low implementation loss
Fully verified and real-time tested on a FPGA based development platform
Considerations for easy ASIC integration
Validated on IPrium Evaluation Boards

可交付内容

VQM/NGC/EDIF netlists for Altera Quartus II, Xilinx ISE, Lattice Diamond or Microsemi (Actel) Libero SoC
IP Core testbench scripts
Design examples for Altera, Xilinx, Lattice, and Microsemi (Actel) evaluation boards
Free 1 year warranty and support period