Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC
10G I.3 BCH Encoder/Decoder for ITU G.975.1
特色
- Fully synchronous design, using single clock
- Fully synthesizable drop-in module for FPGAs
- Optimized for high performance and low resources
- Low implementation loss
- Fully verified and real-time tested on a FPGA based development platform
- Considerations for easy ASIC integration
- Validated on IPrium Evaluation Boards
可交付内容
- VQM/NGC/EDIF netlists for Altera Quartus II, Xilinx ISE, Lattice Diamond or Microsemi (Actel) Libero SoC
- IP Core testbench scripts
- Design examples for Altera, Xilinx, Lattice, and Microsemi (Actel) evaluation boards
- Free 1 year warranty and support period
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Encoder
- JPEG, H.264/AVC, H.265/HEVC (SHVC) and VP9 Encoder
- VP9, H.265/HEVC, H.264/AVC and JPEG Encoder
- AV1, VP9, H.265/HEVC, H.264/AVC and JPEG Encoder
- H.264 Baseline Encoder with compressed reference frame store
- VESA DSC (Display Stream Compression) 1.2a Video Encoder
- Lossless & Near-Lossless JPEG-LS Encoder