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Process IP Listing

9373 IP Cores (1681 - 1720)

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Linear Regulator IP, UMC 40nm LP process

1.8V and 1.2V input, loading 360mA, 1.1V output with VBG=0.88V Regulator with BYPASS mode, UMC 40nm LP/RVT Low-K Logic process.

1681
Linear Regulator IP, UMC 40nm LP process

3.3V to 1.1V/100mA REG, Linear Regulator, UMC 40nm LP/RVT Low-K Logic process.

1682
Linear Regulator IP, UMC 90nm SP process

2.5V to 1.2V/100mA REG, Linear Regulator, UMC 90nm SP/RVT Low-K Logic process.

1683
Linear Regulator IP, UMC 90nm SP process

3.3V to 1.0V/100mA REG, Linear Regulator, UMC 90nm SP/RVT Low-K Logic process.

1684
LVDS Receiver IP, 500Mbps, UMC 55nm LP process

LVDS RX IO PAD 500Mbps, UMC 55nm LP/RVT Low-K Logic process.

1685
LVDS Tx IO IP, 1.25GHz, UMC 90nm SP process

Single Port LVDS Transmitter PAD 1.25Gbps, UMC 90nm SP/RVT Low-K process.

1686
MIPI D-PHY Receiver IP, 80Mbps - 1.5Gbps, UMC 40nm LP process

MIPI Receiver 80Mbps-1.5Gbps, UMC 40nm LP Low-K Logic process.

1687
MIPI D-PHY Transmitter IP, 80Mbps - 1.5Gbps, UMC 40nm LP process

MIPI Transmitter 80Mbps~1500Mbps combo with CMOS input, UMC 40nm LP Low-K process.

1688
MIPI D-PHY Transmitter IP, 80Mbps - 1.5Gbps, UMC 40nm LP process

MIPI Transmitter 80~1500MHz with 1-clock lane, 4-data lanes, UMC 40nm LP/RVT/LVT Low-K process.

1689
MIPI D-PHY Transmitter IP, 80Mbps - 1.5Gbps, UMC 40nm LP process

MIPI Transmitter 80Mbps~1.5Gbps with 1-clock lane, 2-data lanes, UMC 40nm LP/RVT/LVT Low-K process.

1690
MIPI D-PHY Transmitter IP, 80Mbps - 1.5Gbps, UMC 40nm LP process

MIPI Transmitter 80Mbps~1.5Gbps, UMC 40nm LP/RVT/LVT Low-K process.

1691
One Port Register File Compiler IP, Bit-cell: 0.425um2 (HVT), Support retention and deep sleep modes with built-in power gating circuitry., UMC 55nm LP process

UMC 55um LP Low-K process One Port Register File compiler.

1692
One Port Register File Compiler IP, HJTC 0.18um pFlash process

HJTC 0.18um pFlash process synchronous Single Port Register File memory compiler.

1693
One Port Register File Compiler IP, UMC 0.11um HS/AE process

UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process synchronous high density Single Port Register File SRAM memory compiler.

1694
One Port Register File Compiler IP, UMC 0.11um HS/FSG process

UMC 0.11um HS/FSG Logic process, One Port Register File memory compiler.

1695
One Port Register File Compiler IP, UMC 0.11um HS/FSG process

UMC 0.11um HS Logic process synchronous Single Port Register File memory compiler.

1696
One Port Register File Compiler IP, UMC 0.11um LL process

UMC 0.11um LL/FSG process synchronous Single Port Register File SRAM memory compiler.

1697
One Port Register File Compiler IP, UMC 0.13um HS/FSG process

UMC 0.13um HS/LL fusion (FSG) process high density synchronous Single Port Register File SRAM memory compiler.

1698
One Port Register File Compiler IP, UMC 0.13um HS/FSG process

UMC 0.13um HS/FSG Logic process synchronous Single Port Register File SRAM memory compiler.

1699
One Port Register File Compiler IP, UMC 0.13um LL process

UMC 0.13um LL Logic/FSG process high density synchronous Single Port Register File SRAM memory compiler.

1700
One Port Register File Compiler IP, UMC 0.13um SP process

UMC 0.13-micron 1.2V high speed (HS) Logic process synchronous Low Power Single Port Register File SRAM compiler.

1701
One Port Register File Compiler IP, UMC 0.18um G2 process

UMC 0.18um GII Logic process synchronous Single Port Register File SRAM memory compiler.

1702
One Port Register File Compiler IP, UMC 0.18um LL process

UMC 0.18um LL Logic process synchronous Single Port Register File SRAM memory compiler.

1703
One Port Register File Compiler IP, UMC 0.25um process

UMC 0.25um Logic process synchronous Single Port Register File SRAM memory compiler.

1704
One Port Register File Compiler IP, UMC 28nm HLP process

UMC 28nm HLP/UHS One Port Register File compiler with peripheral LVT.

1705
One Port Register File Compiler IP, UMC 28nm HLP process

UMC 28nm HLP/ Low-K One Port Register File.

1706
One Port Register File Compiler IP, UMC 28nm HLP process

UMC 28nm HLP Logic process One Port Register File with LVT.

1707
One Port Register File Compiler IP, UMC 28nm SP process

UMC 28nm Logic process synchronous Ultra high speed Single Port Register File SRAM memory compiler.

1708
One Port Register File Compiler IP, UMC 40nm LP process

UMC 40nm LP One Port Register File with Sleep/retention/Nap mode feature.

1709
One Port Register File Compiler IP, UMC 40nm LP process

UMC 40nm LP One Port Register File with Sleep/Retention/Nap mode & peripheral LVT feature.

1710
One Port Register File Compiler IP, UMC 55nm eFlash process

UMC 55nm eFlash One Port Register File with Power Gating.

1711
One Port Register File Compiler IP, UMC 90nm SP process

UMC 90nm Logic standard performance process synchronous high density Single Port Register File SRAM memory compiler.

1712
One Port Register File Compiler IP, UMC 90nm SP process

UMC 90nm SP/RVT low_K Logic process synchronous One Port Register File.

1713
Oscillator IP, Output: 5KHz, UMC 55nm SP process

Output frequency 5KHz. Input 0.9V-1.1V, Oscillator, UMC 55nm SP/RVT Low-K Logic process.

1714
PLL IP, Input: 25MHz, Output: 156.25MHz, UMC 40nm LP process

Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency is 25M for Low-Jitter Mode, 156.25M for JitteRClean Mode. UMC 40nm LP Low-K Logic process.

1715
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, HJTC 0.18um eFlash/G2 process

Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, HJTC 0.18 eFlash process.

1716
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process

Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.

1717
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 300MHz - 600MHz, UMC 90nm SP process

Input 10M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.

1718
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process

Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process.

1719
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process

Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process.

1720

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