Linear regulator with ultra low quiescent current for retention applications, DELTA standard
You are here:
One Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP One Port Register File with Sleep/retention/Nap mode feature.
查看 One Port Register File Compiler IP, UMC 40nm LP process 详细介绍：
- 查看 One Port Register File Compiler IP, UMC 40nm LP process 完整数据手册
- 联系 One Port Register File Compiler IP, UMC 40nm LP process 供应商
Memory IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- HBM Subsystem IP Gen2
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm)
- sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
- sROMet compiler - Memory optimized for high density and high speed - compiler range up to 2M
- GDDR6 Memory Controller