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TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link

• Universal LVDS-based interfaces supporting variety of Tx and Rx configurations.

On-Chip IO to Core Voltage Buck Regulator

• Input voltages of 2.5V, 3.3V.
• Available output currents to 100mA.

SerDes Hard Macro-IP in GlobalFoundries 22FDX

• Low-power, flexible and robust Serializer-de-serializer IP built upon a proven ring-PLL based architecture

LPDDR5 IP - High performance and low power

• Support LPDDR5 up to 6400Mbps
• Support Channel equalization with 1-tap DFE

eUSB 2.0 PHY for TSMC N3A

• Compliant with eUSB2 specification rev 1.1
• Can be used in USB Host, Device, and Dual Role applications

1GHz to 3GHz, 6MHz to 100MHz Fractional-N Phase-Locked Loop

• TSMC SiGe BiCMOS 180nm
• Output clock frequency range from 6MHz to 100MHz
• Output LO frequency range from 1GHz to 3GHz

12-bit, 9.2 GSPS Analog-to-Digital Converter

• 12-bit Resolution
• 9.2 GSPS Sampling Rate
• 6 GHz Input Bandwidth

CH-6xx CryptoManager Hub

• NIST CAVP hardware classic cryptographic accelerators (AES, SHA-2, SHA-3, RSA, ECC), a NIST certified TRNG behind a highly efficient multi-channel DMA based AMBA interface.

FPGA Proven PCIe GEN6 Controller

• Supports up to x16 link width
• Support for Tx/Rx cut-through
• Supports 32 GT/s and 64 GT/s precoding

32 kHz RC low-drift oscillator in TSMC 22ULL

• High accuracy
• Low power
• Fast wake-up

MIPI D-PHY Receiver with PPI

• TSMC 12nm FFC Process
• Complies with the MIPI D-PHY interface Specification, version 1.2
• HS (High Speed) and LP (Low Power) mode supported

LDPC Encoder / Decoder

• Full hardware
• performance/gatecount
• configurable generator matrix

Smart Network-on-Chip (NoC) IP

• Smart NoC automation
• Topology generation with minimum wire length
• Scripting-driven regular topology creation

Clock Attack Monitor TSMC

• Input frequency: Up to 100 MHz
• Relative frequency measurement capability
• Relative frequency measurement resolution (frel): 10kHz

TSMC GF Intel Samsung Fractional-N Frequency Synthesizer PLL

• Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
• Input & output frequency ranges greater than 1000:1

5G LDPC Encoder / Decoder

• CRC encoding
• Filler bits insertion/removal
• LDPC encoding (basegraph1 and 2, all Z-values)

GDDR7 Memory PHY for TSMC N3P

• JEDEC JESD250C standard compliant
• Advanced process node
• East-West and North-South orientation

5 GHz 250 fs jitter Phase Locked Loop IP Block

• Input Frequency: ~100MHz
• Output Frequency: 5 GHz
• RMS Jitter: <250 fs
• Supply Voltages: 0.8 V (Core), 1.8V (IO)

LDPC Encoder / Decoder

• Full hardware
• performance/gatecount
• configurable generator matrix

Multi-protocol SerDes PMA in FDSOI (GF22FDX FDX 22FDX) - PCIe1 PCIe2 PCIe3 PCIe4 and more

3GPP LTE Turbo Encoder

12-bit SAR ADC TSMC

TSMC GF Intel Samsung Deskew Frequency Synthesizer PLL

32 kHz RC low-drift oscillator in TSMC 22ULL

• High accuracy
• Low power
• Fast wake-up