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Logic based Hardware Root-of-Trust - Physical Unclonable Function (PUF)

• Secure provisioning
• Secured identities
• High entropy seeds

On-Die PDN Analyzer for Transistor-Level Visibility and Telemetry

• Transistor-level PDN visibility
• PDN telemetry and onboard analytics across the silicon lifecycle

10G Base T Ethernet PHY

• CAD Proven database
• Ready to go for fabrication and characterization
• ASIC volume production ( in future)

LPDDR5X/5/4X PHY IP on TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps

Audio Sample Rate Converter

• Studio-Grade Audio Quality
• Scalable and Efficient
• Fast Synchronization

Lightweight Root-of-Trust

• Rapidly implement secure boot and attestation capabilities without significant area, cost, or complexity overhead.
• Prevent malicious software attacks, unauthorized access, and firmware tampering to safeguard critical device functionality.

2kx8 Bits OTP (One-Time Programmable) IP, TSM- 40ULP 1.1/2.5V Process

• Small IP size
• Low program voltage/current
• Low read voltage/current

Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)

• Ultra Low Standby Current
• .72V to .88V
• Internal Bist Mux

Image processing specialized NPU

• Highly Optimized for CNN-based Image Processing Application
• Fully Programmable Processing Core
• 16bit Floating Point Arithmetic Unit

DDR5 PHY IP for TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard DDR5 SDRAMs up to 8400 Mbps

13-bit, 80 MSPS Analog-to-Digital Converter IP Block

• 13-bit resolution
• 80 MSPS sampling speed
• Bandwidth: 2 MHz around Fs/4

MIPI CSI-2

• (SROI) Smart Region of Interest,
• (USL) Universal Serial Link,
• (AOSC) Always-On Sentinel Conduit,

TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link

• Universal LVDS-based interfaces supporting variety of Tx and Rx configurations.

Register File with low power retention mode and 3 speed options

• Ultra-Low Leakage: High VT (HVT) and low leakage HVT (LLHVT) devices used with source biasing to minimize standby currents while operating at low voltage.

UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect

• Emerging Standard Knowledge
• Flexibly Configurable
• Best in Class PPA

DiFi IP core

• Supports: Signal Data, Flow Control, Signal and Version Context Packets
• Integrates Easily with UDP/IP Ethernet Stack through the AXI interface

12-bit, 5 GSPS ADC on GF 22FDX

• 12 bit resolution
• 5 GSPS sampling rate
• 6 GHz Input Bandwidth

Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

TSMC GF Intel Samsung Fractional-N Frequency Synthesizer PLL

• Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
• Input & output frequency ranges greater than 1000:1

Universal Chiplet Interconnect Express (UCIe) Controller

PCIe 5.0 PHY IP for TSMC N5

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization

5V Library for Generic I/O and ESD Applications TSMC 12nm FFC/FFC+ process.

• Targets up to 8A applications
• >8kV HBM
• Silicon Proven

Crypto Coprocessor with integrated Post-Quantum Cryptography IPs

• Scalable architecture and crypto engines for optimal performance/resource usage
• Configurable for perfect application fit
• 100% CPU offload with low latency and high throughput

13-bit, 80 MSPS Analog-to-Digital Converter IP Block

• 13-bit resolution
• 80 MSPS sampling speed
• Bandwidth: 2 MHz around Fs/4