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I3C Host Controller v1.2

• Compliant with MIPI I3C Specification v1.2
• Compliant with MIPI I3C HCI Specification v1.1
• Supports up to 12.5 MHz operation using Push-Pull

AV1/HEVC/AVC/VP9 Video Decoder HW IP 8K30fps@500MHz

• High-quality encoding
• Improved bandwidth efficiency
• Low delay encoding

MIPI C-PHY v2.0 D-PHY v2.1 RX for TSMC N6

• Compliant with the MIPI D-PHY specification, v2.1
• 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
• Compliant with the MIPI C-PHY specification, v2.0

Safety Enhanced General Purpose Neural Processing Unit (NPU)

• Hybrid Von Neuman + 2D SIMD matrix architecture
• 64b Instruction word, single instruction issue per clock
• 7-stage, in-order pipeline

Logic based Hardware Root-of-Trust - Physical Unclonable Function (PUF)

• Secure provisioning
• Secured identities
• High entropy seeds

On-Die PDN Analyzer for Transistor-Level Visibility and Telemetry

• Transistor-level PDN visibility
• PDN telemetry and onboard analytics across the silicon lifecycle

10G Base T Ethernet PHY

• CAD Proven database
• Ready to go for fabrication and characterization
• ASIC volume production ( in future)

LPDDR5X/5/4X PHY IP on TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps

Audio Sample Rate Converter

• Studio-Grade Audio Quality
• Scalable and Efficient
• Fast Synchronization

Lightweight Root-of-Trust

• Rapidly implement secure boot and attestation capabilities without significant area, cost, or complexity overhead.
• Prevent malicious software attacks, unauthorized access, and firmware tampering to safeguard critical device functionality.

2kx8 Bits OTP (One-Time Programmable) IP, TSM- 40ULP 1.1/2.5V Process

• Small IP size
• Low program voltage/current
• Low read voltage/current

Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)

• Ultra Low Standby Current
• .72V to .88V
• Internal Bist Mux

3DIO PHY IP for TSMC N5

• Optimized for heterogeneous integration in 3D stacking
• TSMC N5

TSMC CLN22ULP 22nm DDR DLL - 160MHz-800MHz

PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 40LP

FTP Non Volatile Memory for Standard TSMC 40nm ULP

• Ultra Low Power Read (30uA/MHz for 39b-IO) at 0.85V Single Power
• 10-Time Programmable
• > 10 years retention

NVM MTP NeoMTP in TSMC (180nm, 90nm)

5.5 MHz RC oscillator

External NAND Flash Protection

• Designed to protect external flash memory and its stored assets

LPDDR5/4/4X PHY in TSMC (16nm, 12nm, N7, N6, N5)

V-by-One 1.4 Transmitter

180nm MTP Non Volatile Memory for Standard CMOS Logic Process

• 10K-Time Programmable (MTP)
• > 10 years retention
• Uses standard CMOS process with no additional masks

Nand Flash Controller

ONFI 3.2 NV-DDR2 PHY in GDSII