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7 μW always on Audio feature extraction with filter banks

• µW power consumption
• Integted Voice Activity Detection
• Running on a 32kHz clock in the always on domain

Cryogenic Contact Programmable ROM qualified down to 4K operating temperature

• Specially Engineered CryoCMOS IP
• Characterised down to 4°K
• Minimal Power Dissipation

Ultra Low Latency 100G MAC/PCS for edge AI supports Ultra Ethernet

• Ultra Low Latency
• Supports ULTRA Ethernet Standard

LPDDR4/DDR4/DDR3 PHY - TSMC 22nmULL

• TSMC 22 nm Logic Ultra Low Leakage Process
• Power Supply: 1.1V, 1.2V, 1.5V(dependent on DDR type), and 1.8V
• Metal Stack Option: 1P8M5X2Z with RDL

PCIe 5.0 PHY for TSMC N3P

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
• Lane margining at the receiver

MIPI D-PHY TRx (80-2100Mbps) 14nm

• MIPI D-PHY spec v1.2 compatible
• Synchronous link between Master (data source) and Slave (data sink)
• All lanes support high-speed transmission in the forward direction

Audio-Grade DC/DC Buck Converter in GF 22FDX

• Supply noise-sensitive audio blocks via an ultrasonic mode: 25 kHz switching frequency clamping
• High efficiency, PFM modulation

4x I2S/TDM Configurable Serial Audio Transceiver

• All I2S/TDM streams share the same audio clocks, but can support different data formats
• Runtime configurable audio formats: multi-channel serial audio (TDM) and also I2S, Left-Justified, and Right-Justified

8.5GHz Fractional-N/SSC PLL

• 4nm Low Power Plus (LN04LPP) CMOS device technology
• Dual power supply of 1.2V±10% and 0.85V+5% ~ 0.75V-10%
• Operating junction temperature(Tj): -40°C ~ 125°C

Combined Voltage and Current Reference

• 3σ 4% untrimmed voltage reference accuracy.
• 0.5% variation over -40ºC to 125ºC after trimming.
• 70dB low frequency PSRR.
• 1.24V voltage reference.

Ultra Low Power Embedded SRAM on TSMC 16FFC

• Delivers both dynamic power savings and static power savings compared to industry standard SRAMs
• Ideal for replacing current SRAM IP and delivering SoC-wide power benefits

HBM3 PHY IP for TSMC N4

• Supports 2.5D-based JEDEC standard HBM3 DRAMs with data rates up to 9600 Mbps
• 16 independent 64-bit memory channels

UCIE 2.0 Controller

• Compliant with UCIe 2.0 specification
• High bandwidth and low latency controller design

DDR3/ 3L/ DDR4/ LPDDR4 PHY, TSMC 22nm ULP/ULL Technology

• Compliant with JEDEC DDR3, DDR3L DDR4 and LPDDR4 Standards
• Compliant with AMBA APB 3.0 for register accessing

UCIe and BOW Universal PHY

• Novel Redundancy for Hi-Rel,
• Support for 16&18-bit wide data,
• Support Synchronous Operation,

Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

1.6T Ethernet UMAC

• Low latency, cut-through datapath.
• Simple programming and bringing up sequence matching previous UMAC generations.

12-bit SAR ADC TSMC

12bit 5Msps low power SAR ADC IP core

12-bit, 4 GSPS High Performance IQ ADC in 22nm FD-SOI

• GF22FDX Process
• 12-bit resolution, 4GSPS update rate
• Dual ADC configured as IQ Pair

Multi-protocol SerDes PMA in FDSOI (GF22FDX FDX 22FDX) - PCIe1 PCIe2 PCIe3 PCIe4 and more

USB4 PHY in TSMC (N7, N6, N5, N4P, N3E, N3P)

12-bit 12-Gsps ADC

• 12-Gsps peak sample rate
• 12 bit resolution (10-bit option)
• SMALLER than competing solutions

PCIe 6.0 PHY in TSMC (N6, N5, N4P, N3P, N3E)