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MIPI M-PHY TSMC40LP
The INNOSILICON MIPI M-PHY transceiver is compliant with MIPI M-PHY spec, v0.80.00. It supports both master and slave roles in HS1P, HS1S and LS operation. The M-PHY uses the MIPI standard M-PORTs Protocol Interface to simplify controller integration and supports DigRF v4 and UniPro MIPI protocols.
The architecture is customizable and allows support from 1 to 4 lanes for increased throughput. It is designed with ease of integration in mind. The PHY is small, low power and contains all IOs including primary and secondary ESD.
The architecture is customizable and allows support from 1 to 4 lanes for increased throughput. It is designed with ease of integration in mind. The PHY is small, low power and contains all IOs including primary and secondary ESD.
特色
- Compliant with MIPI M-PHY V0.8
- HS1P, HS1S and LP modes
- Supports DigRF v4 and UniPro MIPI protocols
- Up to 5.0 Gb/s data transfer rate per lane
- TX drivers are programmable for:
- Amplitude
- Slew rate
- De-emphasis
- Auto-calibrated on-die termination
- Spread spectrum clocking (SSC) with:
- Spectrum offset
- Range shape
- Skew rate
- Advanced Rx equalization
- Includes BIST, loop back & boundary scan
- Loop back has 7 different modes
可交付内容
- We can provide the following deliverables to aid quick and reliable integration into the design flow. Please contact us for any additional views:
- GDSII
- Netlist (Spice format for LVS)
- Footprint (LEF format)
- User documentation
- Module integration guidelines
- Datasheet
- Silicon validation report
- Evaluation board
查看 MIPI M-PHY TSMC40LP 详细介绍：
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- 联系 MIPI M-PHY TSMC40LP 供应商