MIPI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
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MIPI M-PHY TSMC40LP
The INNOSILICON MIPI M-PHY transceiver is compliant with MIPI M-PHY spec, v0.80.00. It supports both master and slave roles in HS1P, HS1S and LS operation. The M-PHY uses the MIPI standard M-PORTs Protocol Interface to simplify controller integration and supports DigRF v4 and UniPro MIPI protocols.
The architecture is customizable and allows support from 1 to 4 lanes for increased throughput. It is designed with ease of integration in mind. The PHY is small, low power and contains all IOs including primary and secondary ESD.
The architecture is customizable and allows support from 1 to 4 lanes for increased throughput. It is designed with ease of integration in mind. The PHY is small, low power and contains all IOs including primary and secondary ESD.
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