LPDDR4/3/2 DDR4/3/2 Combo PHY TSMC 22ULP

The INNOSILICON DDRn IP Mixed-Signal LPDDR4/3/2 DDR4/3/2 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low power and high speed (up to 1333Mbps for LPDDR2/3, up to 1600Mbps for DDR3, and up to 2667Mbps for LPDDR4/DDR4) applications with robust timing and small silicon area in 28nm process. It supports all JEDEC LPDDR4/3/2 &DDR4/3/2 SDRAM components in the market. The PHY components contain DDR specialized functional and utility SSTL and HSUL_12 I/Os from 200Mbps up to 1600Mbps (DDR3) and 2800Mbps(DDR4) in 28nm, critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control for any SDRAM interface.

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