MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
SDRAM DDR4/3/2 & LPDDR4/3/2 Hardened PHY - TSMC 40nm ULP_EMF
In addition, our PHY IP is optimized to provide a complete solution when combined with Dolphin s DDRx and LPDDRx SDRAM Memory Controller IP.
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